Clock performance can be affected by noise on its power supply, especially in designs using high-speed clocks, ADCs, or other timing-sensitive circuits. A regulator may provide the required voltage, but that doesn’t necessarily mean the clock is seeing a clean supply.
I wanted to start a discussion on how designers approach power delivery for clocks and other sensitive circuits.
A few factors can influence the noise reaching the clock:
- Regulator PSRR: Higher PSRR helps attenuate noise coming from the regulator input.
- Input and output impedance: Noise currents interacting with the impedance of the power path can create voltage disturbances at the clock supply.
- Decoupling: Proper capacitors can reduce the impedance seen by the regulator and sensitive load.
- Resonances: Inductors, ferrite beads, capacitors, and other parasitics can create high-Q resonances that increase noise instead of reducing it.
The key is to look at the entire power path, rather than evaluating the regulator by its PSRR specification alone.
The block diagram below shows a typical test setup for measuring clock phase noise and power supply jitter.
From a PCB design standpoint, a few practices can help reduce power-supply noise reaching sensitive clocks:
- Keep the regulator-to-clock power path short and low impedance.
- Place appropriate decoupling capacitors close to the clock power pins.
- Consider both the regulator’s input and output impedance when selecting and placing capacitors.
- Check whether ferrite beads or inductors introduce unwanted impedance peaks or resonances.
- Avoid sharing the clock supply with other dynamic loads that can introduce significant current variations.
- Verify the regulator’s PSRR over the frequency range that matters for the application, rather than relying only on the nominal or low-frequency value.
One important point is that adding a capacitor or ferrite bead does not automatically make the power supply cleaner. The interaction between the components and their parasitics can create resonances at certain frequencies.
For particularly sensitive clocks, ADCs, or RF circuits, it can be useful to validate the power network rather than relying only on the regulator datasheet.
Look at:
- Power-supply noise across the relevant frequency range
- Regulator input and output impedance
- PSRR at the frequencies where noise is present
- Transient response from nearby dynamic loads
- Clock phase noise or jitter under different power-supply conditions
If multiple dynamic circuits share a regulator or power path, check whether their current variations are coupling into the sensitive clock supply.
For a deeper look at how power-supply noise, regulator PSRR, impedance, decoupling, and resonances affect clock jitter, read our article Power Supply and Jitter Optimization for Clocks.
