Hi Steve! Can you share tips to match impedance in the PDN, particularly in high-speed digital designs?

Are power integrity simulations or modeling tools used to analyze and optimize the power distribution network? What insights do these simulations provide?

Hello Steve! How is the grounding strategy implemented to minimize ground bounce and ensure a low-impedance return path for the power distribution?

Hello Steve! How is current density managed in power traces and planes to ensure they can handle the required currents without voltage drop or excessive heating?

How is thermal management addressed to prevent overheating in components and traces, especially in PCBs with high power density?

Hi Steve!

Can you explain the use of decapitalization techniques to reduce voltage fluctuations during transient load changes?

What testing methods and equipment can you recommend to validate PI, including measurements of voltage ripple, noise, and transient response?

Hi Steve. Can you discuss the selection of components, such as voltage regulators and filters, based on their impact on PI?

How can I establish my current return paths to minimize ground bounce and maintain power integrity?

Hi Steve,

How does a PCB design handle transient changes in power demand or sudden load spikes? What design elements would you say are crucial for ensuring a rapid and stable response?

Hello Steve, How are decoupling capacitors selected and placed in the PCB to minimize voltage ripple and noise? What factors influence the choice of capacitor values?

This is a good question! This obviously depends on the PDN current and when you get above 1000Amps it can get tricky. We manage copper weight and layers. When we assess this inside a simulator, like Keysight Pathwave ADS, we can see the current density, voltage drop and even temperaure rise all at the same time

Decoupling capacitors are used to cancel the impacts of PCB inductance. Maintaining a low Q PDN generally means that the decoupling capacitance, C is equal to L/R^2 where L is the inductance and R is the PDN impedance. The capacitors are located at PCB resonant locations and/or the point of use (close to the chip). Simulators help a lot with this. The PDN network also generally acts as a low pass filter due to these small inductive terms and this greatly attenuates the ripple. It’s important we use EM simulation for these reasons

PCB’s are inductive by nature (for the PDN). This doesn’t allow fast transient currents and that is where the decoupling capacitors come in. The short term energy comes from these capacitors. A flat impedance PDN is optimum and this means carefully designing the VRM for a specific impedance, but also then choosing the correct decoupling capacitors to absorb the high frequency inductance (C=L/R^2). In many PDN’s the challenge is that the decoupling capacitor ESR is much lower than we want it and that can result in higher impedance resonances closer to the high speed package.

For high thermal impact designs, we include electrothermal analysis so that we can see temperatures. Most of our higher power boards are water cooled or refrigeration cooled and then we can pull the heat from the PCB if we want to. Otherwise it is really only copper distributing the power. We can manage the copper thickness, but active cooling is more efficient.

The PDN impedance is generally inductive. We determine the impedance to match as target impedance (or from an impedance measurement close to the ASIC). We then try to set a Q of 1, which means C=L/R^2, where R is the impedance to match and L is the PCB inductance. Simulation helps a lot with this, particularly for larger, more distributed boards. I do have some videos online about the decoupling. In particular, see the How to Design for Power Integrity videos.

Decoupling capacitors are used to cancel the impacts of PCB inductance. Maintaining a low Q PDN generally means that the decoupling capacitance, C is equal to L/R^2 where L is the inductance and R is the PDN impedance. The capacitors are located at PCB resonant locations and/or the point of use (close to the chip). Simulators help a lot with this. The resulting PDN impedance will hopefully be fairly flat and at a magnitude that minimizes the voltage excursions, maintaining them within allowable limits

both modeling tools (VRM’s, for example) and power integrity simulators are used. Together they provide insight into impedance, transient response, board temperature rise, current density, etc. More modern tools allow optimizations based on criteria, such as minimum number of part numbers, lowest cost, highest performance, etc. ASIC voltage limits are getting very narrow and it can be difficult to obtain the required transient response, but these simulators provide the best tools.

Great question, since this is much of what my company does. The PDN design is generally performed based on a target impedance and capacitors are selected based on impedance. For this reason the first, most essential instrument is a low frequency VNA. We have many application notes, presentations and videos about measuring the impedance.

The transient load is more difficult, because to be meaningful it has to be fast, and ideally support the full thermal performance limit. Picotest has a complete range of solutions all the way to 2,000Amps.

For the ripple, noise, see my Signal Integrity Journal article