For higher current designs this is generally thin interleaved plane layers. Different types of components present different challenges. For example a large CPU is generally pretty slow coming out of the package while some FPGA’s, transceivers and memories offer little in the way of filtering.
We optimize the ground bounce in an EM simulator, managing the decoupling and also the plane inductance.
I have a few papers, articles and videos on the subject, mostly relating to the VRM (search Selecting the VRM). The VRM is the foundation of the flat impedance and is more often poor than good. Learning to manage this first level goes a very long way. I don’t like “filters”, but see my paper Designing Power for Sensitive Circuits. The other major selections are bulk and decoupling capacitors. I do have a lot of papers on it and many other similar answers here. It’s C=L/R^2, so manage the inductance and try to choose capacitors that result in an ESR close to the flat impedance goal
Thank you, Steve!
Steve Sandler
Managing Director
Tel: 877-914-7426 x8
Email: Steve@picotest.com
Web: www.picotest.com
Thanks Steve!