On your via stub resonance calculator, what is the guideline of the resonance freq vs. the frequency of interest (e.g., max harmonics) that you decide if a stub resonance frequency is acceptable or not?
To ensure minimal signal attenuation, it’s crucial that the stub’s first resonant frequency exceeds the fifth harmonic. Ideally, the first resonant frequency should be equal to or greater than the seventh harmonic.
Can you back drill into a buried via, or is it done on thru-vias only?
Yes, you can back drill a buried via.
Does the via need to be calculated according to the impedance?
It would be better if the via is designed per the impedance requirement, especially when designing vias on high-speed tracks.
What copper pour is connected to on TOP ?
The copper pour on the top is the ground plane here.
How do you determine the distance between the GND stitching?
The spacing between these holes should be at least 1/10th wavelength of the highest frequency you aim to shield.
How much power plane is lost due to via stitching being done in excess?
It depends on the via counts and clearances. A higher number of vias generally leads to more significant power plane loss as each via introduces additional resistance and inductance. While, larger clearances between the via and the power plane edge result in lower power losses.
What is the difference between via shielding and ground stitching?
Via shielding involves placing a row of vias close to a signal trace. Meanwhile, ground stitching vias create an array of vias that connect various board layers to a common ground plane. The goal is the same for both techniques: reducing EMI and stabilizing the ground reference.
After backdrilling, is there a via plugging process afterwards?
Typically, after back drilling, vias are plugged using either solder mask or non-conductive fill materials. This process ensures structural integrity and prevents signal interference or contamination.
For BGA and best mfg considerations, I have been told that if you are doing via in-pad for any of the BGA pins, you must do it for all.
The statement is not accurate. In PCB design, the decision to use VIP is based on various factors such as signal integrity requirements, thermal management, and manufacturing constraints. It’s a design choice rather than a mandate.
Also, if doing a via-in pad for the BGA, are there any mfg pros to doing SMD pads instead of NSMD?
Yes, using SMD (Solder Mask Defined) pads instead of NSMD (Non-Solder Mask Defined) pads for BGAs when implementing via-in-pad has manufacturing advantages. This choice helps prevent solder mask material from seeping into the sides of the via holes during manufacturing, which is particularly beneficial when dealing with thicker copper layers.
Is this different from via fanout?
Yes, BGA fan out and via fan out are not the same. BGAs have extremely fine-pitch spacing between pads, and it’s difficult to make direct connection with traces. Hence, fan out technique connects the numerous small pads of a BGA to the wider traces on the PCB. While, via fan out connects a single via to multiple traces on the same layer of the board. This can be useful for distributing signal and power from a single point to various destinations.
Are via-in-pad microvias filled with CU just by plating or do you employ an additional process?
If the requirement is to completely fill via-in-pad microvias with copper, it involves a distinct process separate from regular plating.
Can you provide the testing results, paper, etc, that cites the “Tenting improves the heat dissipation from thermal components”? I do not know if I understand this statement.
Tenting aids in thermal management by reducing the air gaps surrounding the vias. It mitigates the risk of hot spots and improves the system’s overall thermal efficiency.
1. Which, via filling technique, conductive and non-conductive, minimizes the CTE-related issues and potential fractures effectively?
2. What are the drawbacks if we fill all the vias in a board?
Is the planarization uniform or a spot planarization across the plane??
We planarize the entire panel rather than spot planarization. The primary focus is controlling the material removal process. To achieve this, we utilize advanced planarization machines equipped with flat brushes that efficiently sweep across abrasive materials. Also, we closely monitor the copper thickness throughout the process to ensure uniformity and precision in planarization.
What is the maximum allowable PCB thickness when using Rogers RF or an equivalent dielectric material for a VPX backplane PCB with up to 18 layers?
There isn’t a specified maximum allowable panel thickness when using PTFE materials like Rogers RF for VPX backplane PCBs with up to 18 layers. The limitation typically depends on the capabilities of individual fabricators.
Why are the staggered vias displayed as cone shapes in your stack up?
The cone-shaped vias are easier to plate during the manufacturing process, ensuring reliable electrical connections. Additionally, using cone-shaped vias helps prevent outgassing issues, particularly in laser-drilled vias.
Do we need to specify to plug the microvias?
Yes, it’s important to specify plugging for outer layer microvias. Particularly it’s crucial for outer layer microvias, as they are exposed to environmental factors and solder during assembly, making them more susceptible to damage if left unplugged.
Is your schematic and PCB layout app limited to Allegro?
No, our schematic and PCB layout application is not limited to Allegro. We also support Altium Designer and KiCad to accommodate user preferences and requirements.
What is the typical thickness of an individual layer in a PCB? It appears that PCBs with stacked vias are constructed by bonding layers together one by one.
In a typical PCB manufacturing process, individual layers are typically constructed with core thicknesses ranging from 4 mil to 8 mil during a single lamination job. Layers containing laser vias, however, tend to be thinner, typically falling within the range of 2 mil to 4 mil.