Ask Me Anything with Mark Hughes


Ask your questions in this thread and expert @mjhughes will reply on March 27th!

Hello Everyone! I’m quite happy to answer any questions you have about your projects, my projects, or something else entirely!

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I don’t have a specific question coming to mind but what would you say is the best way to cut down manufacturing costs? where would you start?


Hi @Lieniner , Thanks for the question!

If I have one rule that works in my favor, every single time, is that I will ALWAYS multi-quote a project. I’ll send the RFQ out to three different fabricators that I trust to get the job done and I’ll let them compete against one another for the job.

That said – I’ve already got relationships with these fab houses so I know their capabilities – that’s incredibly important. Heck – go out and tour the factory if you can and absorb as much as you can.

If you’ve never designed a board before, the first place to start is to learn how boards are made. Learn about all the different processing steps, and the ways boards are put together. Every additional step is going to increase the time, increase the risk, and increase the cost of fabrication.

If you don’t know how boards are made, you’re not going to understand why blind and buried vias are more expensive than through-hole vias. A lot more expensive. One story I like to tell is that of a friend – he noticed a job that had a single buried vias. Just one. He talked to the designer and helped him move things around so that it was a through-hole via instead. Saved over $50k on a multi-panel order.

(Sorry for the ramble – it was something of an open-ended question)


Do you know how the buried via became a TH? What did you move around to make that happen ?

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No, I don’t know the answer for that particular job. I just know they found the board space to make it happen – depending on how tightly that board was routed, that could mean moving one thing and being done in five minutes, or it could mean moving dozens or a hundred things and it taking 1/2 a day.

You’ve got to decide when it makes financial sense to do so. Ordering 1 panel? Hard to say – likely 1-2 hours of your PCB Designers time is worth more than what you’ll save on the board order. Ordering 1000 panels? You can keep your designer busy processing changes for weeks and still save money.


Do you have any tips to save money on panelization?


Hi Mark. Are there any test and equipment tools you could recommend that are not so pricey. I’ve been thinking of starting a home lab since Covid.


Hello Mark
What is the most cost effective way to build a PCB that has both power components and BGA on the board? Heavy copper like 2oz gets in the way of fine pitch BGA . Should I fanout the BGA with vias in pad or try to use narrow traces with small vias through the board. What are are the limits to via size, trace width and clearance and how does this impact the power components?


That’s going to come with a big, fat “It depends” It depends on what you’re trying to do, and it depends on what your budget is.

When you say equipment, are you asking for regular equipment that you might find on an EE’s desk/workstation, or are you saying “I want to get my own pick and place” too?

I’ll start answering what I’d expect to find in a regular EE lab and then you can guide me with your response.

For home-lab equipment, a few favorites.

Small Parts Storage: Aidetek boxes.
Get a label maker & tweezers for label application if you get these boxes.

For low-freqency LCR measurements:

or even lower-frequency (and cheaper):

For low-frequency / low-bandwidth oscilloscopes: Rigol DHO800 series: DHO800 Compact Size, Various Interfaces | RIGOL

For low-cost / high-stability power supply: Rigol DP832

For Pliers/Cutter – Vampliers 5" mini screw extraction pliers, 5.5" precision mini needle nose, 5.5" mini long-nose pliers:

For magnification/viewing: Digital Microscope: and or Olld school lighted magnifying glass w/ stand:

For tweezers:

For soldering Iron: Pinecil w/ extra tips

I can keep going – just have to let me know if this is what you had in mind, or if you were thinking of something else. The tools listed above are in my “go-bag” for when I’m taking tools to a location. My personal lab-bench at home has different things (a JBC Soldering station instead of Pinecil, for example), but the nicer stuff comes at a premium price.

And – to be clear – I’m not necessarily listing any tools because they’re the best-in-class – but they’re the cheapest I would buy and still use. You can get cheaper, but if it breaks quickly or is a pain to use, you’re going to not use it, and it’s a waste.

If you’re doing serious projects, like for example, chasing 1V/ps rise times in GaNFETs, you’ve got no choice but to spend money and buy better test equipment.

I look forward to your response

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Yes! In fact I do! There are a few things that come to mind:

First thing is this – unless you know what you’re doing, you might as well let your PCB fabricator do it. There’s no additional cost for the service, and if something is wrong, it is a problem for the fabricator. If you do the panelization, and there’s something wrong, it’s a problem for you.
That being said, it’s not all that difficult a process to figure out. Panels are usually 18" x 24", and your fab house will use either 0.5" or 1" margins, leaving you with 17" x 23" or 16" x 22" of usable area. I’ll use 16" x 22" as it is quite common and the easiest to demonstrate math.

Panelization is about quantity and preparing for depanelization/individualization of the boards.

Let’s start with quantity. Unless you’re doing castellation or another edge-plating process, fabricators require you to keep your copper-to-edge distance ~20 mils from the board-edge, and your components ~40 mils from the board edge (note: These numbers can vary from fab-house to fab-house). Further, the minimum board-to-board clearance for a routed design is around 100 mils. now you can’t do anything about the ~20 mil copper-to-edge distance. But if you use v-score instead of routing, you’ll gain 100 mils per board.

Assume that you’ve got a 2" x 2" rectangular board. On a v-score design, you can fit 9x11, or 99 boards on a panel. On a routed design, you need 0.1"+2.1" per board. 16=0.1+2.1x, 22=0.1+2.1y, or x=7 and y=10 (you have to round down). Now you’re at 70 per panel. In this example, we can increase yield by 43% per panel. Now, there are times you have to route your board. That’s just the way it goes, but figure out what your usable areas are so you can maximize yield. No sense in leaving unused fiberglass unless you’re size-constrained by another aspect of your product – like a case. You can also do a combined route/v-score, but that’s an additional process and an additional cost.

Remember I said you have to keep your boards together past the assembly process? Well, the trouble with packing 99 2"x2" boards on a panel doesn’t really happen during fabrication – on fabrication, it’s fine. Assuming the panels survive shipping intact, the trouble happens when you go to stuff those boards and send it through a reflow oven. Most pick and place machines can handle a full-sized panel. Most reflow ovens, not so much. The heat is going to start at one end of the board and cause that part to expand, And with a bunch of length-wise cuts, that panel is going to start to sag between the rails, and the v-scores are weak points where failure is likely to occur. If you’ve cut a bunch of horizontal and vertical slots all across your board, the chances of spontaneous individualization in the reflow oven is pretty high. A technique you can use is called skip-scoring/jump-scoring. And if you do it right, it will help your panel maintain rigidity during fab & assembly, but when you start taking the edges of the panel away (the 0.5" tooling margin), then the rest of the boards should fall away easily.

Google isn’t returning a result on Sierra’s site for jump/skip-scoring. I’ll let them know it might be a good article topic!

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Hello @henry.kroker and welcome to the community!

You’re right – heavy copper and fine-pitch BGA don’t play well in the same sandbox. I have to ask – how did you determine your copper weight and what is the BGA pitch, pin-count, and pattern?

Here’s why “how” is important. IPC-2221 is wrong. Not a little, but a lot. IPC-2152 supplanted it a few years ago, and you’ll find w/ IPC-2152, you need far less copper than IPC-2221 recommends. We can get into why – but basically, the numbers were made up and no one did the math until Mike Jouppi and IPC-2152 came around. Even then, the numbers are often more conservative than they need to be.

Here’s why “BGA-pitch” matters – as you already seem to be aware, in a subtractive manufacturing process the heavier the copper, the more your trace-width and space-width minimums need to be, and on “fine-pitch” BGAs – say 0.5 mm pitch, you might be able to get one trace out if you use a subtractive manufacturing process. On a large BGA, that can lead to a lot of PCB layers. Combine that with heavy copper, and you’ll be paying for someone’s new boat. There are new additive manufacturing processes that can definitely get two traces through, even between 0.35mm pitch BGAs, but they’re not fast, and might be incompatible with the heavy-copper.

Without knowing more about your project, I’m going to offer two ideas you might not have thought of yet.

  1. Have you considered an interposer board? Create a small 4-8 layer 0.8mm thick board (or thinner) that has the original BGA pattern on one side, and a wider-pitch BGA pattern on the other. Costs for one via-in-pad is the same for 10,000 vias-in-pad. It might make sense to make that interposer board with the vias-in-pads packed 1000x more efficiently than if you do the BGA on the same board. Talk to your assembly house about how they would want to handle the assembly before you go this route.

  2. Let’s say the math is right and you need 2 oz/ft² of copper for your high current design. And let’s say that’s 2 oz is 100 mils wide on layer 1. Well, you can split that up so it’s 1 oz, 100 mils wide on layer 1 and 4. Or 0.5 oz, 100 mils wide on layers 1, 2, 3, and 4. You’d want to provide a ton of via stitching for thermal purposes, and of course a path for displacement current, but copper is copper – it can run on the surface, or beneath. (I’ll add the caveat, if you’re dealing with crazy voltages / very high currents, you can’t always do this).

Hope this helps – if not, please let me know more about your project.

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Hey Mark, I just wanna add one thing here, sometime hardware designer picked the 0.4/0.35mm packages unnecessarily, where you needs that micro via. However similar devices can be found in bigger packages, like SOT, SOIC etc and you could create room in your layout to accommodate that package and eventually it eliminates the need of using micro via/bb via.


That’s a good point Syed! Thanks for sharing it!

Thanks for the suggestion! I’ll get my team started on this.

Thanks Mark !

I like both of your suggestions and I did not know there was such a dramatic change in IPC-2152.

The interposer idea is quite feasible and could even be implemented with mouse bites as there are not a lot of traces actually being used (eMMC memory) but the multilayer staked power concept is also good. That will work fine for the slower power parts for sure and I will check out this change in the IPC standards you mentioned…

wow thanks I did not expect such a personal response!


I’m not going to post a link here, because it might be considered bad form. But if you google “Mike Jouppi” there’s a series of three webinar videos that might interest you. One of them has a simple thermal calculation worksheet you can use to determine the number of vias you’ll need when transitioning layers.

I think Mike is retired now – but you could probably convince him to consult a couple of hours on your project if needed. He’s a super nice guy – wish our careers had overlapped more.

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We love Mike here so please feel free to share these links. :slight_smile:

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One other thing Syed – feel free to jump in on any question. You might have better answers than me on some of these topics :slight_smile:

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