When do you remove non-functional pads in a multilayer design, and when do you leave them? Some fab guidelines say to remove them to avoid stub effects and improve signal integrity, while others keep them for mechanical strength. I’m not sure what actually drives the decision in practice, is it mostly about frequency/rise times, or are there other factors?
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The decision balances signal integrity, mechanical reliability, and fab capability, not just frequency.
Remove non-functional pads when signals have edge rates under 1 ns or when via stub length starts approaching λ/10, since rise time matters more than clock frequency in practice. Removing them also gives you more predictable via impedance by eliminating layer-dependent capacitance variables, which simplifies modeling. A lot of fabs actually prefer removal anyway for drill wear and yield reasons, so it’s worth confirming their preference early.
Keep them when vias carry power, ground, or low-speed signals where the SI impact is negligible. On high aspect-ratio vias above 8:1, keeping one or two selective pads can help with barrel anchoring without giving up all the SI benefits. Flex and rigid-flex are a special case where NFPs anchor plating to flexible layers, so retain them even on high-speed nets to avoid plating separation. If IPC Class 3 requirements apply, IPC-2222A defaults to retention and removal typically needs explicit designer authorization, so check that before stripping them.
Default to removing on high-speed and RF nets, keep on power, ground, and low-speed. On thick or high layer-count boards, consider keeping one or two per via for mechanical stability where SI allows. Always add about NFP in the fab notes .
When genuinely unsure, a quick SI simulation with and without NFPs usually settles it. The impedance and crosstalk numbers tend to make the answer pretty clear.. Theory says remove for SI, but in practice your fab’s preferred default for yield and process control often drives the final call.
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Thanks, this clarified a lot. I was mostly thinking about SI, but the fabrication and reliability constraints is something I hadn’t fully considered. Another thing I’m curious about is whether HDI and sequential lamination designs change the usual approach to non-functional pad removal.
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Fab shops prefer to remove unsupported (unconnected) lands for fabrication reasons even if you include them in outputs. If you prefer to have them maintained, be sure to specify that in your notes. Myself, I mostly remove unsupported under most normal layouts. I use Altium and that ECAD tool defaults is to remove unsupported lands at gerber generation. That way the tool maximizes the clearance copper to adjacent plated holes.
Some users remove the unsupported lands during layout with the intent on allowing adjacent copper closer to the holes but one needs to be careful not to increase fabrication risks by tightening the copper clearances to adjacent plated holes too much under those conditions. I prefer to avoid this method under most conditions.
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Yes, HDI and sequential lamination definitely change the approach. In HDI builds, microvias and thin dielectric layers already reduce stub-related effects significantly, so the SI benefit of removing non-functional pads is sometimes smaller than it is on conventional through-hole vias.
At the same time, sequential lamination introduces additional registration and plating reliability considerations, especially with stacked vias and thin core materials. Because of that, fabs may be more conservative about removing pads on certain layers compared to a standard multilayer build. In practice, HDI designs tend to rely more heavily on the fabricator’s process recommendations rather than applying a universal remove all NFPs rule.
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One factor to consider is testability and rework. Keeping some non-functional pads can provide additional copper anchoring around vias during thermal cycling and repeated soldering operations, which may matter more on boards expected to see rework or field repair. This is more of a concern on thicker multilayer boards where repeated localized heating can stress the via barrel. So in some cases, the decision is influenced not only by SI or fabrication yield, but also by how the product will be assembled, inspected, and serviced over its lifetime.
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Resin flow and voiding during lamination can factor in too. Removing large number of non-functional pads shifts the copper distribution across the stackup, which affects how resin fills around dense via fields under press. On boards with uneven copper balance (in multilayer design) some fabs will actually want to keep certain pads just to hold layer structure consistent and avoid lamination defects.
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Another practical consideration is thermal behavior during assembly and rework. Non-functional pads add extra copper mass around the via barrel. On dense via fields or thicker high-layer-count boards, this can affect local heating rates during reflow soldering or hand rework. Removing them can sometimes improve thermal uniformity and reduce the risk of uneven heating or hot spots in large via arrays. That said, the impact is usually secondary compared to the dominant factors (signal integrity on high-speed nets, via reliability, and fab/lamination preferences). In practice, it matters more on boards with heavy thermal cycling requirements or frequent field rework.
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