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| Question | Answer |
|---|---|
| mSAP is an additive process, so how does copper foil roughness play a role here? | It still matters significantly, just as it does in a subtractive process. In mSAP, we start with an extremely thin copper foil, approximately 1.5 µm, as the seed layer. Even though most of the final copper is built up through plating, the initial copper surface still influences copper deposition, adhesion, and the final surface topology. |
| With 2 mil width and spacing, is there a trace length restriction? | There is no specific trace-length restriction from a technology standpoint. As the process matures, improvements in production control, surface quality, and adhesion will allow us to maintain these fine features reliably over longer trace lengths. |
| To follow up, if the traces are built up by the additive process, doesn’t this mean that their surface will be very smooth and the roughness of the base material will play less of a role? | Not necessarily. Surface roughness still matters because we need to deposit copper onto the seed layer and ensure sufficient adhesion between the layers. It also influences the final copper topology. Therefore, controlling the starting copper surface remains important even in an additive process. |
| Do you have a recommended cross-section tab layout? | Not specifically. We automatically populate what we refer to as the process frame. This includes all the in-process inspection coupons, via structures, and other required test features. These are automatically generated based on the PCB class and manufacturing requirements. All we need from the customer is the actual board design files. The supporting coupons and test structures are then automatically scripted and incorporated into the manufacturing panel, so the customer does not need to define them separately. |
| Doesn’t material performance vary from one PCB supplier to another based on their experience and process choices? How do you compensate for this when designing? | We control this through our production controls, including the approved Bill of Materials (BOM) and Approved Vendor List (AVL). By controlling the materials and qualified suppliers, we can maintain consistency in material performance and ensure that the design is manufactured using validated material and process combinations. |
| Do you expect the customer to provide the panel fiducials, or do you add those reference points? | We add the panel fiducials as part of our manufacturing process. This allows us to establish the appropriate registration references for imaging, drilling, and other fabrication steps. |
| What’s the % of glass-resin the prepreg must have in HDI for Class 3, so that we do not have issues in the field? | Currently, we use materials similar to those used in conventional subtractive HDI processes, and there isn’t a single, defined resin-content percentage for Class 3 HDI. Instead, it is a balance among several factors: achieving the target dielectric thickness, providing sufficient resin to prevent resin starvation, and controlling CTE to support via reliability. The appropriate resin content therefore depends on the specific stack-up, materials, and reliability requirements. |
| How do we normally minimize warpage when laminating PCBs with more than 10 layers? | From a design standpoint, the biggest factor is stack-up symmetry. Maintaining a balanced, symmetric stack-up—where the top half mirrors the bottom half—generally helps minimize warpage. Avoiding hybrid constructions with multiple dissimilar materials can also reduce the risk. If an asymmetric or hybrid stack-up is unavoidable, the specific stack-up should be modeled to predict and manage warpage during lamination. |
| How many microvias can you stack? Some PCB manufacturers say they can do all layers. | The number of microvias that can be reliably stacked depends partly on the dielectric material and the type of build-up film being used, including whether the material is reinforced or non-reinforced. From a manufacturing standpoint, stacking four to five microvias can generally be achieved without significant difficulty. However, the practical limit depends on the overall design and reliability requirements. In some applications, we limit the stack to two microvias because higher stacks may not pass our reliability testing. Ultimately, the appropriate microvia structure depends on the end application and its reliability requirements. |
| For HDI, do you drill first the layers where the HDI is found, layer by layer, or do you drill all the layers where the HDI is found? | HDI is manufactured using a sequential lamination process, generally building the structure from the center outward. We laminate the required layers first, followed by imaging, etching, plating, and laser drilling as part of each sequential build-up cycle. We do not drill the layers before lamination. The drilling and subsequent fabrication steps are performed after the appropriate dielectric layers have been laminated. Therefore, when specifying drill sides, it is important to understand the sequential build-up sequence and which side of the panel is being processed at each stage. |
| What is the HDI pad size vs. HDI drill size? | Typically, we allow approximately 2 mil of pad extension on each side of the finished laser-drilled via, resulting in a pad diameter approximately 4 mil larger than the finished drill diameter. We can reduce this depending on the specific design and registration requirements, but maintaining a standard pad size provides a more robust manufacturing process. At very fine geometries, we also need to consider other fabrication factors, such as laser skiving for certain flex materials and the limitations of conventional solder mask processes. At these feature sizes, solder mask registration can become a significant constraint, so alternative approaches may be required depending on the application. |
| I think there is IPC data for HDI now, but we need to see the capability. | IPC does have standards covering HDI technology, and IPC also has a committee working on UHDI-related standards. However, as feature sizes become extremely small, there are manufacturing considerations that are not fully captured by a standard alone. Actual manufacturing capability and process control become increasingly important. One significant challenge at these geometries is solder mask registration. Conventional solder mask processes may not provide the registration accuracy required for extremely fine features. Therefore, at higher levels of density, the manufacturer’s process capability and demonstrated manufacturing results become particularly important. |
| Can UHDI work with embedded technology, for example, Ticer/Omega? | Yes. UHDI can be combined with embedded technologies such as Ticer/Omega. The feasibility depends on the specific embedded structure, material system, stack-up, and manufacturing requirements, so the overall design should be evaluated to ensure compatibility between the technologies. |