Thanks for your interest in our EMC-compliant stack-up webinar with special Q&A by Kenneth Wyatt.
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Still need to switch out Karen for me in the body. 
Kenneth Wyatt
Windsor, CO
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Oops… done. 
I had a meeting come up, so will have to miss this. Hope to watch the recording! Thank you
| Question | Answer | Answered by |
|---|---|---|
| When working with different, let’s says for this question, types of memory in a design, the datasheets or application notes usually contain recommendations for the stack-up. How can all these different recommendations, including the ones given here, be incorporated? | When discussing stack-ups, I like to follow two basic rules that have been recommended by experts who have trained me: * Every signal layer should have an adjacent solid return plane. * Every power trace or power layer should also have an adjacent solid return plane. I know that routing power for memory interfaces can be challenging, but if you follow these two fundamental principles, you are unlikely to go wrong. I’m sure we’ll be discussing this topic in much greater detail as we go along. I’ve also seen recommended layouts for DC-DC converters in datasheets. In my experience, half or more of these suggested layouts have poor EMC characteristics. They often allow coupling between the input and output current loops, and many do not provide a solid return plane. For that reason, I would not accept a datasheet’s recommended layout without first verifying that it meets the requirements of your specific application. I’m sure we’ll cover this topic in much more detail as we continue. |
Kenneth Wyatt |
| What about ground pours on outer layers while an uninterrupted plane exists on an inner layer? | Ground pours on outer layers are a topic of ongoing debate. Personally, I do not recommend using them unless they are connected to the adjacent solid ground plane with multiple stitching vias. Otherwise, these isolated ground pours can behave like small patch antennas. Another common issue is connecting decoupling capacitors directly to an outer-layer ground pour without ensuring that the pour is solidly tied back to the main ground return plane. This can compromise the intended return path. I also see this frequently in DC-DC converter layouts. Many datasheets show a small ground pour used to connect the input and output capacitors in a buck converter configuration. However, this approach can create unwanted noise coupling between the input and output current loops. For these reasons, although there is considerable debate on the use of ground pours, I personally do not recommend them. |
Kenneth Wyatt |
| Similar question to the last one, in a two layer design, it is ok to use ground pours in both layers connecting them with lots of vias? | Yes, it can be done. However, I would probably not use a two-layer board for any kind of high-performance project or product. If your signals are relatively low frequency with low data rates, then a two-layer board can work. That said, I generally prefer to route the signals and power on the top layer while keeping the bottom layer as a solid ground return plane. I understand that this isn’t always possible, depending on the complexity of the circuit, so you have to be careful with the layout. There are two important things to consider: First, digital signals are not simply the flow of electrons through copper traces. The digital signal itself is an electromagnetic wave that travels through the dielectric. This electromagnetic field is confined between the signal trace and its return plane. If there is any discontinuity in the return path, the electromagnetic field can leak, leading to field leakage, increased crosstalk between circuits, and edge radiation from the PCB. These effects can negatively impact EMC performance. |
Kenneth Wyatt |
| Please give an example of how to avoid isolated plane to reduce board warpage. Is there a specific area size? Is this referring to a dead copper? | There is no specific area size or fixed rule for defining an isolated plane that could cause board warpage. The likelihood of warpage depends on several design-specific factors, including the board size, copper distribution, and stack-up. Warpage analysis is performed by evaluating the complete PCB design. If the design is likely to experience warpage, the manufacturer can recommend appropriate changes to the stack-up or copper distribution to improve mechanical stability. Because many variables are involved, there is no single standard guideline that applies to every design. From an EMC perspective, however, it is advisable to be cautious with large isolated (floating) copper areas, especially on the top and bottom layers. Unconnected copper patches can potentially behave like re-radiating patch antennas, depending on the frequencies and harmonic content present on the board. While the behavior of isolated copper within the internal layers is less certain, it may also contribute to unwanted coupling. For these reasons, I would be cautious about using large isolated copper patches and would generally prefer copper thieving techniques where additional copper balancing is required. |
Steve Carney and Kenneth Wyatt |
| The problem I’ve seen here is components connecting to the pour, but the pour has one via connecting to the return plane some distance from the components, making a long return path and increasing inductance | Yes, that is exactly the risk of using ground pours on the top and bottom layers. Components are often connected to the ground pour, but if the pour is connected to the solid ground plane through only a single via located some distance away, the return current must travel a longer path. This longer return path increases series inductance, which is undesirable in PCB design because it can degrade the return path and increase the overall level of electromagnetic interference (EMI). To avoid this issue, ground pours should be well connected to the solid internal ground plane using multiple stitching vias placed close to the connected components, ensuring a short, low-inductance return path. |
Kenneth Wyatt |
| What is your definition of annular ring size? Do you define the annular ring as the remaining copper between the pad edge and the finished plated hole diameter, or between the pad edge and the drilled hole diameter before plating? |
The annular ring is defined as the amount of copper remaining between the drilled hole and the outer edge of the pad. In other words, it is measured from the drilled hole diameter (before plating) to the edge of the pad, not from the finished plated hole diameter. You can think of the pad as the target, with the drilled hole centered within it. The annular ring is simply the copper surrounding the drilled hole that remains after drilling. |
Steve Carney |
| What about filling in the gaps on the external layers with GND pours? | From an EMC perspective, using ground pours on the outer layers can be somewhat risky if they are not implemented properly. One common issue is that designers may connect components to the ground pour but fail to provide multiple vias to connect the pour to the solid ground reference plane. This can result in a poor return path. Another concern is that isolated or poorly stitched ground pours can behave like unintended radiating antennas, potentially increasing electromagnetic emissions. For these reasons, I generally discourage the use of ground pours on the top and bottom layers unless they are carefully designed. Ground pours can certainly be used, but they should be connected to the solid internal ground plane with multiple stitching vias arranged in a grid pattern. This ensures the ground pour remains at the same potential as the reference plane and minimizes the risk of EMC issues. |
Kenneth Wyatt |
| In addition to the question, What about ground pours on the outer layers when an uninterrupted ground plane exists on an inner layer?, I have another question: If L1 and L2 are closely spaced, with L2 being a solid ground plane, would you pour power rails (e.g., 3.3 V or 1.5 V) on L1? Let us assume that L3 is located approximately 4–5 times farther away from L1 than L2. Would there be any EMI or signal-integrity concerns with routing or pouring power on L1 in this case? |
Yes, this approach is perfectly acceptable. You can route signals and pour power rails (such as 3.3 V or 1.5 V) on Layer 1, provided that Layer 2 is a closely spaced, solid ground plane. As long as Layer 1 is tightly coupled to the adjacent ground plane on Layer 2, there are no significant EMI or signal integrity concerns with routing or pouring power on Layer 1. The power is referenced to the solid ground plane, which provides a well-defined return path. In a typical 4-layer PCB, Layers 2 and 3 are usually separated by a relatively large dielectric thickness (approximately 30–40 mils in a standard 1.6 mm (62 mil) board). This wider spacing is common and does not affect the suitability of routing power on Layer 1, as long as the Layer 1–Layer 2 spacing remains small. However, if you intend to route signals and power on Layer 4, it is preferable to make Layer 3 a solid ground plane as well. The two ground planes should then be stitched together at multiple locations using vias to provide a continuous, low-impedance return path and improve EMC performance. |
Kenneth Wyatt |
| Is it workable if several signal layers are referenced to the same ground plane? The signal layers would be on either side of the ground plane. For example, signal - [prepreg] - ground plane - [prepreg] - signal - [core] - signal or power - [prepreg] - ground plane - [prepreg] - signal . | Yes, this is a workable and recommended stack-up approach. Multiple signal layers can share the same solid ground plane as their reference, with signal layers placed on both sides of the ground plane. This follows two fundamental stack-up design principles: Every signal layer should have an adjacent solid return (ground) plane. Every power plane or routed power layer should also have an adjacent solid return plane. Therefore, stack-up arrangements such as Signal–Ground–Signal or Signal–Ground–Power are both valid and work well. A single ground plane can serve as the reference plane for the layers on either side, providing a well-defined return path for signals. In other words, using the same ground plane as the reference for signal layers on both sides is perfectly acceptable and is a common, effective stack-up practice. |
Kenneth Wyatt |
| Between Sig and RRP gap is >0.2mm for better coupling this is good but what about between RRP and PWR in standard 1.6mm board, what is the best board thickness for 4 layer (S/G/P/S) for both low and highspeed signals? | A 4-layer stack-up of Signal–Ground–Power–Signal (S/G/P/S) is commonly used, but it is not the preferred choice for high-speed or EMC-critical designs. The main concern is that the bottom signal layer is referenced to the power plane instead of a solid ground plane. Since most digital circuits use the ground plane as their return reference, signals routed on the bottom layer must find a way back to ground. This often requires decoupling or stitching capacitors to provide a return path between the power and ground planes. While this approach can work, it introduces additional EMC risk. For low-speed applications, an S/G/P/S stack-up is generally acceptable and is widely used. However, it is not recommended for high-performance or high-speed designs, especially those with high clock frequencies or Gigabit data rates. A better approach for high-speed designs is to ensure that both signal layers are referenced to solid ground planes. For example, stack-ups that use signal and routed power layers adjacent to stitched ground planes provide much better return paths and EMC performance. Regarding the spacing between the ground and power planes in a standard 1.6 mm (62 mil) PCB, the separation is typically around 30 to 40 mils, which is relatively large. This wide spacing reduces the high-frequency capacitance between the planes, making the inherent plane-to-plane decoupling less effective. Ideally, the power and ground planes should be much closer together, with a dielectric spacing of approximately 3 to 7 mils. Closely spaced planes form a large distributed capacitor, providing better high-frequency decoupling and improving power integrity. |
Kenneth Wyatt |
| If keeping a solid return plane always underneath/adjacent to a signal layer, how do I keep the stackup balanced so that the board doesn’t potato chip? Especially at higher layer density builds. | In most cases, this is not a major concern, provided the copper distribution remains reasonably balanced. Problems typically arise only when there is a significant imbalance in copper thickness, for example, using ½ oz copper on signal layers and 2 oz to 4 oz copper on plane layers. During fabrication, the PCB is manufactured in panel form, and the stack-up is evaluated along with the actual board design. If the design is likely to warp or potato chip, adjustments can be made within the stack-up to reduce the stresses that cause warpage. The key factors are: Keep the copper thicknesses reasonably balanced across the stack-up. Use adequate dielectric thickness, as thicker dielectrics generally improve mechanical stability. Maintain a balanced copper distribution, as the amount of remaining copper on each layer also affects warpage. PCB manufacturers can calculate the copper balance and predict whether the design is likely to experience warpage. In most designs, especially those with balanced copper weights, this is not a significant issue. Interestingly, higher-layer-count, higher-density boards are often easier to keep mechanically stable because the copper is distributed more evenly throughout the stack-up. As long as extreme copper imbalances are avoided, maintaining a solid return plane adjacent to signal layers while achieving a balanced stack-up is generally not a problem. |
Steve Carney |
| How do you balance the desire to keep a system chassis isolated from the PCB signal ground and the need to ground the shield for coax cables? The coax shield wants to be bonded to the chassis and also connected to the system ground. Can’t connecting these cause EMC issues? | The answer depends on the type of product. Many products use a bare PCB inside a plastic enclosure, so a chassis ground is not applicable. However, for products with a metal, shielded enclosure, the chassis becomes an important part of the EMC strategy. While there may be specific reasons to isolate the PCB signal ground from the chassis in some designs, in most high-speed systems it is generally better to mount the PCB solidly to the chassis. This provides a low-impedance reference and improves EMC performance. Chassis grounding becomes particularly important in applications where ESD protection is critical. When an electrostatic discharge strikes an I/O or power connector, you want the ESD current to flow directly to the chassis rather than through the PCB circuitry. For this reason, it is common practice to provide a chassis plane or partial chassis ground around the I/O and power connectors. This area should be securely bonded to the metal enclosure at multiple points to create a low-impedance path for ESD currents. Although the chassis plane can be extended across the entire PCB, at a minimum it should cover the I/O and connector regions where external cables enter the system. For coaxial cables, the preferred approach is to use chassis-mounted coax connectors or feed-through connectors. The connector should be bonded directly to the chassis, ideally with an appropriate gasket to maintain shielding effectiveness. This is important because allowing cables to penetrate a shielded enclosure without proper bonding violates a fundamental EMC design principle. In practice, the coax shield is typically connected to the digital ground while also being bonded to the chassis through the chassis ground layer. The chassis layer is then securely connected to the metal enclosure. The same principle applies to USB, Ethernet, and other I/O connectors—their connector shells should be well bonded to the enclosure so that ESD currents have a direct, low-impedance path to the chassis instead of flowing through the PCB. This approach helps maintain shielding effectiveness while minimizing EMC issues by providing a controlled path for high-frequency and ESD currents. |
Kenneth Wyatt |
| I usually route high-speed buses on one layer and power on another layer with a reference plane in between to minimize layers. Can I route both high-speed buses and power on the same layer, keeping my reference plane uninterrupted? | Yes, this is a valid approach. You can route high-speed signals on one layer and power traces on another layer, provided they are separated by a continuous, uninterrupted ground plane. The ground plane serves as the reference plane for the high-speed signals, allowing their return currents to flow directly beneath the traces. Meanwhile, the power return and transient currents flow on the opposite side of the ground plane. Since the signal and power return currents are separated by the ground plane, they have minimal interaction, helping maintain signal integrity. As long as the ground reference plane remains continuous and is not split or interrupted beneath the high-speed traces, routing power and high-speed signals on adjacent layers in this manner is a perfectly acceptable and widely used stack-up strategy. |
Kenneth Wyatt |