LDO Regulators Placement

I’m in the process of designing a PCB that includes noise-sensitive components like an FPGA and RF mixer. For the power systems, I’ve opted to chain switching regulators to LDO regulators to minimize heat dissipation and improve noise performance. However, I’m uncertain about the optimal placement of the LDO regulators.

My initial inclination is to position them near the outputs of their corresponding switching regulators to confine switching noise to the board’s edge. Alternatively, placing them near the loads they drive could potentially result in a more accurate voltage across the load, as less of the LDO output voltage would drop across the power traces.

Although my board isn’t overly large, and I have space to widen the power traces, if necessary, I’m leaning towards the second setup. Additionally, I’m not overly concerned about trace inductance because I anticipate that bypass capacitors will address any issues in that regard.

I would appreciate any insights or recommendations on the optimal placement of the LDO regulators in this context. Thank you.

I think I’d opt for placing the LDO’s near their corresponding sub-circuits.

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Here are some considerations based on the components and layout you plan to use. The switcher-LDO cascade is a common configuration, but it’s important to pay attention to the switching frequency in relation to the Power Supply Rejection Ratio (PSRR) of the LDO at that frequency. For instance, if you have a 1MHz switcher like an old 780x, the linear regulator (not an LDO) may not effectively reduce the output ripple caused by the switcher.

The critical aspect is ensuring a robust, low-impedance path for high current (or high dV/dt) between the switcher and LDO. If you have a single low-impedance track, pour, or plane connecting them, you shouldn’t have much to worry about, and your layout can be designed to best suit your needs. However, problems can arise with multiple plane changes or long stubs, which could lead to radiation issues.

Therefore, it’s important to avoid these and ensure proper decoupling throughout the circuit: at the input and output of the switcher, at the input and output of the LDO, and with bulk capacitance between the switcher and LDO.

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To determine the impact on your load regulation, start by considering the inverse load regulation error of the LDO and adding the resistance of your trace and return path. This resistance might be negligible, and in that case, it won’t significantly affect your design.

Typically, the series output incremental or “knee resistance” is about 1 to 2% of the rated voltage/current, which corresponds to your output Load Regulation error. For instance, with a 5V/1A LDO, the resistance would be 5 Ω, and 1% of this is 50 mΩ. The ESR of your output capacitor needs to be much lower than this to ensure the pulse load error is significantly less than the step load regulation error.

To evaluate your pulse load response, consider the trace inductance and resistance, which influence ringing or noise. The output impedance (Zout) of the LDO increases with frequency due to the decreasing loop bandwidth for negative feedback inside the LDO, reaching unity at a certain breakpoint. This characteristic helps reduce the Q factor of pulse noise resonance.

Since RF circuits are generally sensitive to supply noise, compare the impedance of the tracks with the impedance of a low ESR capacitor at the equivalent frequency of the pulse load to determine the peak-to-peak error in DC amplitude. Given a known current pulse duration, track resistance, and inductance (typically 10nH/cm), you can easily compute these values. Usually, the LDO’s location is less critical than the choice and placement of the output capacitor as recommended by the LDO datasheet.

Always start with design specifications for RF Vdc tolerance, ripple, Idc, and Iac versus frequency. Use an impedance or step voltage simulator plot to anticipate and address potential issues. Remember that the output impedance of LDOs increases with frequency.

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When designing a PCB, especially for complex systems, it’s crucial to manage power supply noise and layout effectively. Here are some key points to consider:

  1. LDO Placement and Grounding: LDOs (Low Dropout Regulators) regulate the output voltage relative to their ground (GND) pin. The capacitor placed at the output ensures stability and links the local GND with the output at high frequencies (HF). However, substantial current in the ground plane can cause GND voltage variations across different points. This variation is akin to voltage drops due to trace resistance, underscoring the importance of placing the LDO closer to the load.

  2. Layout of Switching Regulators: Switching regulators (switchers) require meticulous layout planning. Poor layout can lead to excessive noise and ripple, adversely affecting other components.

  3. Load Considerations: Each load on your board can be both a potential noise victim and a noise generator. Assess each load’s current and voltage requirements and their noise tolerance at various frequencies. Additionally, consider the nature of the current drawn by each load—whether it’s constant, spiky, random, or high frequency.

  4. Impact of Specific Components:

  • USB2 Components: These can draw current spikes at specific frequencies (e.g., 8kHz) when processing packets, leading to ripple in the power rails. This can introduce noise in analog outputs, as seen in some USB soundcards.
  • Crystal Oscillators: These may draw constant average current but can turn power supply noise into phase noise, affecting signal integrity.
  1. Power Domains and Filtering: Splitting the board into multiple power domains and using ferrite beads or multiple LDOs can help manage noise. For instance:
  • Microcontrollers: May not be sensitive to supply noise but can generate wideband noise.
  • Operational Amplifiers: Often have good low-frequency power supply rejection ratio (PSRR) but poor high-frequency PSRR. They may draw variable current to support their load.
  1. Implementing Filters:
  • LC Filters: Effective for blocking high-frequency noise while allowing low-frequency noise to pass. Typically used in a Pi filter configuration to prevent HF noise from contaminating the main supply and to provide a small loop for HF current.
  • Combination of LC Filters and LDOs: To address both low and high-frequency noise, an LC filter followed by an LDO can be used. This combination can offer higher PSRR (Power Supply Rejection Ratio) than high-end LDOs alone.
  1. Practical Tips:
  • Use LDOs to smooth out low-frequency ripple and noise, noting that at high frequencies, the pass transistor behaves like a capacitor.
  • For high-current loads, a high-current filter at the switcher output might not be ideal. Instead, use smaller, low-current filters for sensitive parts to minimize core saturation in beads.

By carefully grouping loads, applying appropriate filters, and placing LDOs strategically, you can effectively manage noise and ensure the stability and performance of your PCB design.