Among the high-speed designs we’ve received lately, we see that getting controlled impedance right on the first try is still tricky. Between variations in actual Dk, copper roughness and stack-up tolerances, things drift from what designers seem to originally plan.
Do you rely mostly on your EDA tool’s field solver? Have you found any good ways to double-check your assumptions?
We’ve been using field solver outputs for initial design but always run impedance coupons on the first batch. Even then, we sometimes see 5 to 8% deviation due to copper roughness and resin content changes. One thing that helped was working closely with our board house to lock down stackup details early and specifying the exact resin system. Curious if others push their fab for tighter tolerances or just design guard bands into their traces?
We had issues on a 10L RF board where the vendors assumed Dk didn’t match our actual material batch throwing off our diff pair impedance. Now we use TDR measurements on test coupons for every build and it’s saved us a lot of debug time. But would appreciate any tips on good low cost TDR setups for quick inhouse checks without sending everything out.
Getting controlled impedance right on the first try is indeed challenging given all the variables involved. We’ve found it really valuable to simulate across a tolerance window rather than assuming nominal dielectric and trace values. This helps us understand how close we are to critical boundaries, especially for differential pairs or dense routing layers. For example, modeling a ±10% shift in Dk and a few percent variation in copper thickness gives us a better feel for real-world margin.
We also ask our fabricators for their actual stackup builds with trace width/spacing targets and impedance test results from previous runs with the same materials. That way, we’re not just relying on assumptions—we’re referencing historical performance. Some fabs are willing to share typical TDR plots or process corner data, which can be extremely insightful.
One approach that’s worked well for us is creating impedance test structures on every panel, not just basic coupons, but actual trace geometries used in the design, including layer transitions and via stubs when relevant. This often reveals issues that generic coupons overlook.
We also maintain a database of impedance measurements from completed boards, organized by fab house and material combinations. Over time, this gives us realistic correction factors we can apply during design. It’s surprising how consistent the deviations can be once you start tracking them systematically.
One strategy that has proven effective is involving the PCB fabricator early in the design phase, not just for stackup confirmation, but also for a pre-fabrication review of impedance modeling assumptions. Many board houses possess in-house modeling tools calibrated to their specific processes and materials. These tools can often identify discrepancies between EDA tool predictions and real-world outcomes before fabrication begins. This collaborative review can detected issues, especially with less common materials or hybrid stackups.
Getting impedance right first time is tough, especially with Dk shifts and roughness. We primarily use Allegro’s field solver for initial design but never rely solely on nominal values. We cross-check structures using external tools like the Sierra Impedance Calculator against our EDA results. For critical designs, we simulate across our fabricator’s tolerance bands (Dk, copper thickness) in Hyperlynx to vet margins early. Crucially, we send stackup/target impedances to the fab before finalizing routing, asking them to run it through their process-calibrated calculator and provide achievable trace parameters.