Join our Ask Me Anything about controlled impedance where you can ask us questions on:
• Dielectric materials
• Trace width and spacing
• Stack-up configuration
• And much more!
Question submission window: Through October 30th
What is the recommended trace width/space to meet let’s say 100ohm on diff pairs?
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Why does the width/space for controlled impedance vary so wildly between manufacturers and altium? If it’s simply a function of er and the geometry of the copper and dielectric, it seems that the values should be similar.
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I would like to know how you test the impedance of PCB/Flex circuit for 100 ohm differential pairs.
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We use a Polar Instruments CITS880 TDR system.
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Since Altium is not actually making the PCBs, I’m sure they must be making some assumptions, whereas each mfg. can really fine-tune the geometry.
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How do you verify your customers’ impedance before manufacturing their boards?
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That would depend on the layer thickness and dielectric constant at a minimum. There are other factors that affect it, but those are the two biggest ones.
When the customer sends in his Gerber files we typically perform a DFM screening.
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You should try our Impedance Calculator, it’s free and should give you the answers you’re looking for.
https://www.protoexpress.com/tools/pcb-impedance-calculator/
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Does soldermask impact impedance control?
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Yes. It’s not huge but it’s real. You need to change the Air dielectric of 1 to the effective Dk which is sort of an average of the two values.
What sort of controlled impedance failures do you see in practice? Are there problems hitting 10%, or is it only tighter tolerances? Is it almost entirely design/calculation errors that shouldn’t be expected to work with the specified materials? Or do you have problems with the materials and processing too? If there are material problems, is it usually consistent within a batch? A single panel?
Yes. It’s not huge but it’s real. You need to change the Air dielectric of 1 to the effective Dk which is sort of an average of the two values.
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Remember, we are designing, fabricating, and assembling boards all for other companies. As a result, we never see test results or almost any feedback regarding what we built. To be sure, if there is a PCB related problem we’ll here about it pretty quick. Thankfully those are pretty far in between these days. Some years back, I designed a PCB for a local customer, an eval board for an RF switch IC. When he populated it and tested in their lab on a vector network analyzer, it didn’t pass. Uh-oh. I called Sierra who then sent me their test date. Armed with that I visited the customer confident the problem was likely at his end.
Now, I always like to run a sanity check on complex test set-ups. So many little things can bite you. So I got an attenuator of known value and a F-F SMA, and the first thing was it showed the SMA has having excessive loss. Turned out his test operator saved a cal a long time ago, probably changed the set-up multiple times, and continued using the same cal file for about a year and a half.
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Hitting the required tolerances, especially day after day, with a mix of items as small as a thumbnail or as big as a desktop monitor, and from single sided to over thirty layers can be an impossible task at times. Everything from temperature and humidity to power outages can ruin your plans. While I’m not part of, nor can I speak for, the manufacturing group it appears they are Robin Hood-like accurate and get the bullseye quite a bit. So we specify what we can hit without too many failures, but if you wanted 1% accuracy we can do it – just throw away 95% of the boards and charge accordingly. So if the there is the “one” critical trace let us know and when possible we’ll keep an eye on it.
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The source of errors is distributed across the spectrum, and probably equally. The chemical etching and mechanical drilling all have error bands. The design calculations have error bands, even the test equipment has error bands. So I don’t honestly think there is just a couple items, but if you have any real concerns I’d contact our QA department to see if they have that data.
Again, the people that make the panels get everything right 99%+ of the time. But I’ve never seen a company without some problem, be it process or whatever. But panels due bring new problems. The material can change ever so slightly from panel to panel. The panels themselves vary slightly across their length. It is important to remember fiberglass-epoxy mixes are not homogeneous. If they were pure epoxy or pure glass most of the process would be way easier.
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How to calculate Impedance for flex PCB if the reference layer is hatchet ground plane?
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We do a lot of controlled impedance and don’t see a lot of failures but this wasn’t always the case. The modeling programs work well so no issues with design/calculation and line width and height are easily controlled but the final press-out thickness of the dielectric/pre-preg can be tricky. A signal layer with 15% remaining copper takes a lot more resin to fill than a plane layer with 60-65% remaining copper so there is a balance between the types of adjacent layers, pre-preg resin content and glass style/thickness along with press cycle to get the desired thickness.
Hitting 10% usually isn’t a problem but the tighter the tolerance the more challenging. It’s quite rare to have problems with the actual materials so it mostly comes down to stack-up and press cycle. If we see a stack-up with new variables we will build a First Article panel to test and confirm the impedance model.
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