4-layer board: Top / GND / 3.3V / Bottom. My internal 3.3V plane has a large region that can’t connect to the main polygon without violating clearance rules.
Should I leave this as floating copper for copper balance, or remove it entirely to avoid noise coupling?
I’d generally avoid leaving an electrically isolated 3.3 V copper island, especially near sensitive or RF circuitry, since its coupling can be difficult to predict. If the region cannot be connected to the 3.3 V net without violating clearances, removing it is usually preferable.
If the fabricator needs additional copper for plating balance, they can typically handle that with their own copper-balancing or thieving pattern rather than relying on a floating 3.3 V island.
I’d also be cautious about treating a floating island as harmless just because it has no DC connection. Its capacitance to nearby traces and planes can give it an RF potential, and its behavior depends heavily on its size and surrounding geometry. For EMC-sensitive designs, I’d rather remove the island than leave an uncontrolled resonant structure.
I agree with the others: if the only reason for keeping the island is copper balance, I’d remove it and let the fabricator handle the balance with their normal thieving process. If the fabricator requires designer-provided copper, I’d ask them what pattern they recommend rather than leaving a 3.3 V island floating or arbitrarily connecting it to GND. The correct treatment depends on why the clearance is required and what the island is coupled to.
I’d remove the floating 3.3 V island. In this stackup, L3 is directly adjacent to the Bottom layer, so a large isolated copper region can add unintended capacitive coupling to signals routed on the Bottom layer. That can affect signal behavior depending on the geometry. If the area is only being retained for copper balance, I’d let the fab house handle the balancing with their normal thieving pattern rather than using a floating 3.3 V island.