Clarification on PCB Routing, EMI and 6 kV Surge Performance – Isolated DC-DC Input Stage

Signal and Power EMC and EMI
1

Dear Team,

We have designed an isolated –48 V DC-DC power input stage and would like your guidance on the PCB routing approach with respect to EMI performance and surge immunity.

System Overview

  • Input supply: –48 V DC

  • DC-DC converters:

    • –48 V to +48 V (isolated)

    • –48 V to +12 V (isolated)

  • Maximum input current: 20 A

  • PCB: 14-layer stack-up, compact board size

Input Protection and Filtering

  • Input surge protection

  • Two-stage EMI filter with common-mode choke

  • Inrush current limiting circuit

  • Reverse-polarity protection MOSFET

  • MOSFET output connected to DC-DC module input pins

Routing Strategy

  • From input to filter output:

    • LINE and RTN are routed on the same layer

    • Traces are maintained 2 mm clearance

  • From MOSFET output to DC-DC modules:

    • 7 layers used for LINE and 7 layers for RTN

    • Layer sequence arranged as RTN / LINE / RTN / LINE

  • Via stitching provided near DC-DC module input through-hole pins for current sharing

Stack-up and Copper Details

  • Dielectric thickness between adjacent layers: 0.153 mm

  • Copper thickness:

    • Top and bottom layers: 1 oz

    • Inner layers: 0.5 oz

Isolation and Earth Clearance

  • Isolation earth.

  • Primary to earth clearance on top layer: 2 mm

  • Primary to earth clearance on inner layers: 0.5 mm

Clarifications Required

  1. Is this routing approach effective for differential-mode noise reduction?

  2. Does the multi-layer LINE/RTN structure help in controlling common-mode noise?

  3. Are the isolation clearances sufficient for 6 kV surge immunity?

  4. Is the via stitching near DC-DC input help for EMI ?

  5. Is this approach suitable for meeting CISPR 32 Class A requirements?

Your guidance on the above points will be very helpful.

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2

Is there another requirement that is driving the overall number of layers in stackup? If the layer count is only for increased copper thickness, it might be more cost effective to use less layers, but higher copper weight per layer. That assumes the design can support larger minimum clearances/widths per layer.

I also would be very concerned of your proposed dieletric thickness between each copper layer.

From input to filter, I assume those two nets will be on an external layer. 20 amps will be a lot to push on a single 1oz layer. I expect each net will need to be nearly 1.5 inches wide to handle that much current on a single 1oz external layer.

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