When designing HDI or high-density boards, blind vias help free up routing space and cut down on via transitions, but I’ve noticed some PCB manufacturers don’t list them as a standard capability, or they require extra review before accepting them.
I’m trying to understand the fabrication constraints that make blind vias harder or more expensive to produce than through vias. Which layer combinations and aspect-ratio or minimum-size limits actually push cost and manufacturability, and where the line sits before a fab has to switch processes or reject the design outright.
I’d especially like to understand what PCB designers should consider during layout to avoid creating a blind-via design that the fabricator can’t manufacture economically.
Blind vias cost more mainly because of sequential lamination. A through-hole via drills the entire stack in one pass after final lamination, but a blind via needs its own press cycle before the rest of the layers go on, so each blind-via layer pair effectively adds a full lamination, drill, and plate cycle to the build.
That’s the real cost driver, not the drilling itself. Aspect ratio compounds it: most fabs cap blind vias around 0.75:1 to 1:1 depth-to-diameter before plating uniformity gets unreliable, which is also why blind vias are usually only spec’d L1-L2 or L1-L3 rather than reaching deeper into the stack. Push past that ratio or ask for a blind via spanning more layers, and you’re looking at extra sequential lamination cycles, which is usually the point where a fab either flags the design for review or steers you toward via-in-pad or a buried-via alternative instead.
Blind vias shouldn’t be avoided by default. The key is whether the routing density they provide justifies the additional fabrication steps. If a few blind vias solve a specific escape-routing problem, they may be worthwhile. If they are used extensively without a clear routing benefit, the added fabrication cost can become difficult to justify. It’s best to confirm the proposed via structure with the fabricator before completing the HDI layout.
Another option worth discussing with the fabricator is a 1+N HDI stackup. Depending on the routing density and required via structure, this can sometimes provide the needed escape routing without making the blind vias unnecessarily deep or adding more sequential processes.
For very dense areas, filled and capped microvias can also be useful, particularly for via-in-pad, but the fabricator should confirm the process and cost before committing to the layout.
Before committing to blind vias, I’d first see whether the routing can be simplified enough to avoid them. Moving power and ground to dedicated internal layers, maximizing SMD placement, and optimizing component placement can eliminate a surprising number of via transitions.
I’d also ask the fabricator for their smallest standard via and corresponding pad requirements before starting the layout. Designing around those capabilities from the beginning can prevent unnecessarily aggressive HDI features later.