I’m designing BGA routing of size 0.5 mm.
Initially I used smaller via hole and diameter and track clearance. After validation with Sierra plugin, it warned, that minimum via hole is 0.2 mm, via diameter 0.4 mm and track clearance 0.1 mm. But with such requirements it is impossible(?) to make 0.5 BGA routing. Please advise how to solve this issue.
Which tool/plugin did you use?
If you’re trying to get a quote, you can use our custom quote service: Custom Quote | Sierra Circuits
This will handle your BGA requirements.
Let me know if you need more help.
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Could you please confirm what you have been used initially (Via hole & diameter & trace width & clearance?). Also we like to know more information, what is your copper & board thickness & layer count to confirm whether it is correct.
Via diameter: 0.25 mm / 9.84 mil;
Via hole: 0.15 mm / 5.9 mil;
Trace width: 10 mm / 3.94 mil;
Trace clearance: 0.05 mm / 1.97 mils.
We need min annular ring of 3.5mil on each side for through hole vias.
On external layer, if you followed 0.25OZ foil then need to use min 3mils trace width & 3mil spacing or if 0.5OZ of foil then min 4mil trace width & 4mil spacing required.
On internal layer, if you followed 0.5OZ then need to use min 3mils trace width & 3.25mil spacing or if 1OZ then min 4mil trace width & 4.25mil spacing required.
If it’s not possible to fanout with through hole vias due to multiple pin fan out then you can try with via in pad or microvias as options.
As Lucy mentioned, you can use our custom quote to upload the latest files for the quoting service.
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Many 0.5mm BGA pitch packages force you into HDI connection methods and vias will need likely some variation of buried/blind/via-in-pad via types. The via geometries that you called out are for less complex layouts which this is likely not. If your BGA has removed ball rows, then maybe in those cases you might be able to use larger vias to avoid HDI.
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This is absolutely true. In most cases (with more than about 50 balls), HDI is the only way to deal with 0.5mm.
Back when I worked at TI, I developed something called Via Channel, which was a technology that depopulated balls specifically to avoid this and made it possible to use only 2 routing layers even with 0.5mm pitch BGAs, but sadly the industry hasn’t really picked up on this technology.
The semiconductor industry is usually pretty out of touch with what it takes to make a PCB using one of their parts.
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Some tips will be in a webinar next month: IC Substrate like PCBs versus HDI & Ultra HDI | ICAPE Group
when you have constraints on via sizes and track clearances can be difficult. However, one recommendation is high-density interconnect (HDI) PCBs. They are usually laser-drilled and can be much smaller than traditional mechanical vias. microvias can be as small as 0.1 mm in diameter, which might fit within your design constraints, use via-in-pad also, which can save a lot of space and allow routing more effectively, Consider using embedded resistors and capacitors within the PCB to save space on the surface and allow for better routing, always confirm your design with the manufacturer to ensure all constraints are satisfied and that the board can be reliably produced.