Thanks for your interest in our high-power PCB webinar.
Missed the webinar? Click the link below to watch the recording and get the slides.
| Question | Answer |
|---|---|
| In a dual-component assembly PCB in which there is a logic block on one side and alternating current circuitry on the other side, should the side with higher currents be a 1 oz copper layer and the other 0.5 oz? Or should I ensure symmetry in the external layers? | Maintaining symmetry in the PCB stack-up is critical. Even when one side carries higher currents than the other, preserving a symmetrical structure should be the priority to ensure reliable electrical and mechanical performance. |
| It was mentioned that high-frequency return currents follow the signal trace. What is considered high frequency for the return current? | For return current behavior, “high frequency” refers to the switching speed, not the clock frequency. As a general guideline, any switching speed above 1 MHz should be considered high frequency, at which point the return current will tend to follow the signal trace along its reference plane. |
| Keeping power and ground planes closely spaced was mentioned. How close is needed? | The required spacing between power and ground planes depends on the target impedance of the power distribution network and the project’s cost constraints. |
| In a high-power PCB also working at higher frequency, how can you manage skin-effect AC resistance? Is there anything from the PCB design perspective to minimize it, or is it something high-frequency power electronics needs to deal with (unless using external wires and going to Litz wire)? | From my perspective, the primary concern is not AC resistance but impedance. The switching wavefront defines the design requirements, so the focus should be on controlling impedance rather than treating skin effect as a resistance problem. |
| What if I need to use a PCB section to carry several DC voltages in the range of 5 to 24 V, like in a backplane PCB where DC and AC voltages are present? How should the “islands” be positioned? | Each voltage island should have its own dedicated area and be placed adjacent to a ground plane. From my perspective, accommodating multiple isolated voltage islands in this way will likely increase the required PCB layer count. |
| When designing high-current PCBs where multiple layers are needed to carry current in parallel, is it enough to have one of those planes next to a ground plane, with the thinking that the transient switching fields will flow there, or do we need to at least sandwich those parallel layers with ground on both ends? | In general, high-current designs require a low-impedance power distribution network. Parallel transmission lines are achieved by placing power adjacent to ground in the PCB stack-up. I often use a power–ground–power stack-up because it creates two parallel power transmission lines while maintaining a low-impedance structure. |
| What is considered high voltage (>20 V?) | There is no universal voltage threshold that defines “high voltage,” as it is somewhat arbitrary and depends on the application and industry standards. As a general guideline, I would consider voltages above approximately 48 V to fall into the high-voltage category. |
[P P P P G S] — Would that make sense? |
No. Power does not return on power, and the dielectric between two conductors at the same potential is effectively wasted because no energy exists in that space. This is similar to a cluster of power vias, where nothing is moving in the dielectric between the vias. For energy transfer, what matters is the relationship between the signal and its return path, not between conductors at the same potential. |
| When using a gate driver, I see many example layouts place the gate driver on the same side as the power FETs. This seems to make the gate traces longer. Do you prefer to place the gate driver on the other side and get to the gate through vias? | The key considerations are impedance and transmission line length. The traditional recommendation to place the gate driver on the same side as the power FETs originated when designers were not using ground transition vias. I would not hesitate to place the gate driver on the opposite side of the PCB, provided the signal transitions are accompanied by ground transition vias. With proper ground transition vias, the signal return path remains intact, and the layout performs well. |
| When making high-current PCBs >100 A and designing external bus bars, what is the preferred mounting method: solder, bolt + nut, or press-fit? | The preferred mounting method depends on the industry standards and reliability requirements for the specific application. I would recommend referring to the relevant standards that govern the industry in which the design will be used, as the choice between soldering, bolted connections, or press-fit mounting should ultimately be determined by the required level of reliability. |
| I am in San Diego. How do I work with Sierra? | We’ll reach out to you this week. If your design files are ready, you can send them to me at lucyi@protoexpress.com. |
| In the beginning, you talked about a high-frequency trace having a return path best placed directly below the trace in the ground plane, and that having a notch in the ground return plane can cause EMI issues because the return path has to travel around the notch. Would a trace in the ground plane, instead of a notch, result in the same sort of EMI implications? | A trace in the ground plane is fundamentally different from a notch or split because the key issue is the impedance and changes in the three-dimensional structure of the transmission line. Any change in that structure creates an impedance discontinuity. If the discontinuity is less than one-quarter of the wavelength of the switching speed (or wavefront), it is effectively invisible to the signal. However, breaks in the ground path, such as using a ferrite bead or inductor to create a separate analog ground, cause a significant discontinuity in the way energy moves. Regardless of the intended design, the return current must still find where the grounds reconnect. Instead of crossing the split, it is forced to travel around it, filling the space created by the split. This introduces temporal distortion. Since there is rarely just one signal present, multiple signals are forced into the same return path, increasing crosstalk because crosstalk occurs at the wavefront. As a result, any break in the ground plane can create several undesirable effects. If a break in the ground plane cannot be avoided without adding another layer pair, placing a ground via on each side of the break and routing a ground trace alongside the signal trace creates what is often called a bridge trace. While this is still a discontinuity, if it is less than one-quarter of the wavelength, it is effectively invisible. It has far less impact on the signal than forcing the return current to travel around a split. Even a single missing ground transition via can have serious consequences. It has been observed to cause both EMC failures and functional failures. Ultimately, this is a three-dimensional problem. In addition to the physical dimensions, time must also be considered because the missing element in conventional circuit theory is the time required for energy to move. In reality, these are four-dimensional problems that are often approached from a two-dimensional circuit theory perspective. |