Thank you for your interest in our webinar on opening closed eyes. It was presented by Prof. Eric Bogatin.
Missed the webinar? Click the link below to watch the recording.
You can ask your questions on this thread.
Question
1 Speed generally doubles, even if coding needs to change – but the time between versions varies. What drives this? Economic cycles? Tech breakthroughs?
2 Whether cross talk affect the differential signal?
3 In the slide “ISI closes the eye”, is the channel output also pulse shaped?
4 What is the best way to simulate the signal degradation using non ideal connectors? What is the lowest cost software and VNA, to characterize the transmission path and resulting ISI channel output with non ideal interconnects? What is the best way to get a file out of testing, that the Altium spice engine can ingest?
5 How to calculate the Nyquist frequency for PAM4 signaling?
6 How does an encoding scheme like manchester affect the data jitter?
7 20" long test board, what is the signal voltage level? And differential impedance of the race?
8 What is the best way to easily see the eye differences between different stack-up thicknesses, with the same layout? (ideally in Altium simulation environment)
9 Isn’t changing the conductor width also changing the impedance of the trace?
10 Can you recommend a passive circuit topology I can research for equalization? I’m working on a T1L circuit where bi-directional signal might not work with an active filter.
11 Can FFE be practically implemented passively (for example using wilkinsons)? If so, how many iterations can typically be realized before loss becomes impractically large?
12 Can the SerDes Designer import model files from STM32 downloads?
13 The sum of your taps needs to equal 1, don’t they?
The data rate for each standard is on a roadmap specified by the ad hoc organizing committee for the standard. PCIe has a PCIe interest group that manages the spec. The roadmap is driven by the perceived requirements of the industry and the perceived time frame to develop the needed technology advances.
there is cross talk in diff pairs as in single ended traces. It is a little more complicated to analyze but similar guidelines apply. Increase the channel to channel spacing to reduce diff cross talk.
Yes, the channel output of the clean pulse is the distorted pulse that spreads out into the next bit and the next bit. This is ISI.
Connector vendors provide S-parameter models for their connectors. This is the simplest way of incorporating connector models into system simulations. There are no free tools to do this. But all the high end tools and vendors can do this, such as Ansys, HyperLynx, ADS, Cadence and CTS.
The Nyquist frequency is the underlying clock frequency. In PAM 2 or NRZ, there are 2 bits per clock cycle, so the Nyquist is 1/2 the bit rate. In PAM4, there are 4 bits per clock cycle, so the Nyquist is 1/4 the bit rate. If the bit rate is 56 Gbps, the Nyquist is 56/4 = 14 GHz.
the encoding scheme does not affect clock jitter. The jitter is created by the TRX technology and the interconnect, independent of the encoding scheme.
the signal strength in many of the examples I show is 1 V, but this does not affect the S-parameters or the impedance of the interconnects. All the interconnect properties are independent of signal strength.
Each stack up will have a different impedance and different loss in the channel. You have to extract these S-parameters and bring them into a simulation tool like MATLAB to see the eye. You cannot do it directly in Altium. You could do it in MATLAB, ADS, Ansys and HyperLynx pretty easily.
yes. exactly. This means to keep the diff impedance constant requires you to also adjust the dielectric thicknesses of the layers. This is why exploring design space requires a tool that lets you parameters many terms at the same time.
A simple passive circuit that does equalization is an RC high pass filter- a series C and R. This is a simple starting place.
FFE is an active equalization. It is not easy to delay a signal and then add a fraction of it to the continuing signal stream. Since these are all digital signals. DSP is the way to go.
an STM32 is a micro controller. If you have layout design files, you have to convert them into S-parameters for the MATLAB code to analyze the impact on the signals.
in passive FFE circuits, the taps are attenuators so the total power in all the taps has to add up to 1. But there are many FFE drivers that are active and add some gain to the taps. This allows more power to be transmitted and is very useful in high loss systems.
1 Like
Thank you for taking the extra time to answer these.
1 Like