Thank you for your interest in our webinar on implementing EMC design rules. It will be presented by Ignacio de Mendizábal of Denpaflux and Amit Bahl.
Missed the webinar? Click the link below to watch the recording.
You can ask your questions on this thread.
| Question | Answer |
|---|---|
| Do you see a lot of disconnections or issues with vias due to the Coefficient of Thermal Expansion (CTE/TEC/etc.)? | Yes, there are issues when we do IST or D coupon testing on bare PCBs. At the time of assembly, we can also see some problems. CTE is important from a long-term reliability strategy. And it becomes more concerning when using hybrid stack-ups. Make sure the laminate CTE doesn’t differ much from the copper CTE. |
| What kind of solver do you use for your stackup calculations? 2D Field Solver like Simbeor (Same as Altium)? 3D Field Solver? Equations? | Our impedance calculator is based on the 2D numerical solutions of maxwells eqn. results are very accurate and can be used for manufacturing analysis. |
| Which differential Pair is better, loose coupling, or tight coupling, board under consideration is 56Gbps server board | Choosing loose or tight coupling between differential lines depends on a specific design. However, loose coupling will provide less signal loss than tight coupling, allowing wider traces with greater trace spacing. You can calculate signal losses from Sierra Circuits’ Impedance Calculator for a particular operating frequency. |
| Would you agree that Rise and Fall times are determined by the physical architecture of the drivers? Not by frequency? (I am a bit fuzzy on what controls the short rise/fall times since some ICs can have Low Frequency but fast rise/fall times. Some argue that as frequency goes up, the rise/fall times also have to increase or decrease.) | Yes, that is correct. The rise and fall times are similar. The driver family belongs to a logical family. Therefore, the rise and fall times may vary depending on its characteristics. |
| Is there any way to reduce the Rise/Fall besides variable slew rate ICs? | You can’t reduce the rise time; you can only increase it. The only way to reduce it is to change the logic family and the entire device. |
| Why the trace spacing is defined in therms of W and not in terms of High (distance of trace to reference plane)? | In high-speed PCB designs, there are two ways to avoid coupling. One is increasing the dielectric height. Another option is not changing the stack-up; you can increase trace spacing. |
| I’m not sure I am fully convinced that the Ground Pours being added benefit the spaced tracks as best practice. Could you explain why you believe that it is a best practice? | You can increase the spacing between adjacent signal lines or add a ground pour to avoid crosstalk. Remember, the ground pour must be connected to a ground plane. A floating ground pour may act as an antenna and be a significant EMI source. |
| I have a long power trace that comes from a switching (buck) regulator. It mostly goes to un-populated pull-up resistors. Should I worry about this functioning as an antenna with regard to EMC/EMI? If so, how do I reduce the risk? | Antennas can radiate and filter high-frequency noise. Try to place the components close to each other and avoid long traces. |
| Do you quote the job with an hourly rate and other costs? Also, we would need an NDA in place. | The question is not clear. |
| I think best stackup designer is paper and pencil, supported by Solver later | Yes. If you don’t like manual calculation, then use Sierra Circuits’ PCB Stackup Designer. |