Thanks for your interest in our webinar on protecting RF layouts from noise. It will be presented on April 15th.
Missed the webinar? Click the link below to access the recording and slides.
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heck DFSR service, run dcdiag and repadmin, and ensure AD sync + network are OK.
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| Question | Answer |
|---|---|
| How can I find the capacitor value and placement impact from your PDN calculator? | You can use the target impedance from the PDN calculator as your reference point. This target acts as a benchmark for evaluating your PDN performance. Once you have this value, you can input it into your tool to determine the appropriate number and values of bulk and decoupling capacitors needed to meet that target impedance. At the moment, the calculator does not provide a predefined list or dropdown for selecting specific capacitor values. The selection process still needs to be done externally using simulation and engineering judgment. |
| On multilayer PCBs, when using layer 2 as a ground return, are there concerns with coupling on the VDD next to it? | Using L3 as a VDD plane is acceptable, but ensure the power planes are appropriately decoupled. Also, avoid overlapping power planes in regions where RF traces are routed on L1, as this can increase unwanted coupling. |
| The top layer is the RF signal layer, and the second layer is the ground return. Can the 3rd be a high voltage VDD with minimal coupling? |
It depends on how effectively the VDD layer is decoupled and how well the routing is planned. The dielectric thickness between layers also plays a key role, as does the magnitude of the high voltage, since higher voltages can increase the risk of coupling. |
| On a PCB with RF traces on the top layer, is it better to have a ground pour on the top layer, or no ground pour? | For RF designs, it is generally beneficial to have a ground pour on the same layer as the RF trace. It enables the use of coplanar waveguide (CPW) structures, where the RF trace is surrounded by ground on the same layer. Such a configuration helps improve field confinement, maintain controlled impedance, and reduce radiation and interference. However, the ground pour must be properly designed with appropriate spacing and via stitching to the reference ground plane to achieve the desired performance. |
| You showed a tool to calculate max frequency of a signal based on trace width - is there a formula to calculate this theoretically? | In the Max Via Stub Length Calculator, the signal frequency is determined by the stub length and the effective dielectric constant of the medium. We did not demonstrate a tool that calculates the maximum signal frequency based on trace width. Could you please clarify which tool you are referring to? |
| Is prepreg a good isolator that minimizes coupling between 2 different planes? Or are there different types of prepregs? | Prepreg is indeed a good insulating material and helps reduce coupling between adjacent planes. However, its effectiveness depends on the specific type of prepreg and the overall stack-up design. There are many types of prepregs available, with different resin systems and dielectric constants (Dk) to suit various applications. For example, in RF designs, materials such as PTFE (Teflon-based laminates) are often used because of their stable electrical properties at high frequencies. Prepregs also differ in glass weave styles. Traditional weaves resemble a woven fabric, while spread (or flat) glass is processed to create a more uniform, mat-like structure. Spread glass offers better electrical consistency, improved stability, and is preferred in applications like laser-drilled vias or high-speed/RF designs where minimizing signal variation is critical. In practice, selecting the right prepreg depends on your performance requirements, such as frequency, impedance control, and manufacturability. It’s best to define your design needs first and then choose materials accordingly, or consult your fabrication partner for stack-up recommendations. |
| What is the minimum distance between a via and the edge of the copper you can accommodate? | As a standard guideline, this spacing is typically 8 mil. However, if the design and material setup are optimized, particularly when using spread (flat) glass prepreg materials, this spacing can be reduced to around 4 mil. Hence, achieving tighter spacing depends on proper process control and material selection, so it’s always best to confirm with your fabricator for specific capabilities. |
| How to avoid the PWB wrapping issue if the PWB stackup is A-sym. Using CLTE RF material? |
To minimize PWB warpage, especially with an asymmetric stack-up using CLTE RF materials, the most effective approach is to maintain overall balance in the design. A key factor is balancing copper distribution and thickness across the stack-up, as uneven copper can create mechanical stress during lamination and thermal cycling. In addition, material selection, dielectric thickness, and layer symmetry all play important roles. When reviewing a design, we typically evaluate the full stack-up, including copper weights, material combinations, and construction details. If we identify potential warpage risks, we work with the customer to adjust the design. Factors such as panelization (number of boards per panel) and component distribution can also influence warpage. It’s also important to note that some RF materials are more sensitive to thermal expansion and shrinkage, which can further contribute to warping. Because of these variables, preventing warpage is highly design-specific and requires a holistic evaluation of the stack-up and manufacturing process. |
| I’m new to PCB design and currently learning the basics. I want to understand PDN (Power Distribution Network) in depth. Can you suggest any good resources or places where I can learn this properly? |
Here are some resources that you can check: 1. Decoupling Capacitor Placement Guidelines Every PCB Designer Should Know Decoupling Capacitor Placement Guidelines | Sierra Circuits 2. What is Power Integrity and Power Distribution Network? What is Power Integrity and PDN | Sierra Circuits 3. 4 Common PDN Design Challenges and How to Resolve Them 4 Common PDN Design Challenges | Sierra Circuits 4. Practical Techniques for Ensuring Power Integrity in High-Speed Designs https://www.protoexpress.com/webinars/practical-techniques-power-integrity/ |
| What are the considerations when thermal pads (spoke connections) affect in my RF circuit? | Thermal relief spokes increase the inductance and resistance of the return path, which can degrade via stitching effectiveness, return path integrity, and overall shielding in RF circuits. Wherever possible, use solid ground connections to GND pads to maintain better RF performance. |
| Is there a significant cost difference between partial via fill or full board via fill(Non-conductive fill)? I mean filling all through-hole vias versus a couple, for example, under QFNs. | In the manufacturing process, two different drill files are used. First, all the vias that need to be filled, typically in the 10 to 12 mil range are drilled together. These filled vias then go through a series of processes, including barrel plating, filling, planarization, and finishing, which can make this step relatively expensive. Afterward, the board undergoes another drilling stage, often referred to as the first drill, for the remaining holes. It’s important to note that the filled vias need to be separated from the non-filled ones during this process. |