A very important topic that our team faces regularly and is almost never discussed anywhere in relation to signal integrity is the placement of test points, how to place them on different types of nets without degrading signal integrity; on highspeed nets, on I2C, SPI, UART nets, on high current nets, on Kelvin connections, on RF nets, etc.
Could you please give us your recommandations on this.
Thank you.
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Good point! I think the answer is that you need to use the smallest test points possible, or even extend the pad. But let me check with our experts. 
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@sylvainbattah So I asked Mike Schnecker of Rohde & Schwarz and he says:
“This a common issue. Signal integrity is best measured into a terminated load. That is, terminating the device under test into the measurement equipment. This is usually not possible in many situations as the writer points out. The next best method is to use an active, high impedance voltage probe connected as close to the transmitter as possible. This is true for high speed links and even for low speed ones like I2C although the latter is a bit less susceptible to loading problems. The nice thing about active probes is that they minimally impact the loading. This also works for RF but if there is a coaxial connection, one can use something like a 10 or 20 dB coupler to sample the RF signal with minimal signal attenuation. There are both single ended and differential probes available for this purpose. Unfortunately, there are always parasitic inductance and capacitances associated with any probe tips and connection that will load the signal. Connecting to the transmitter output minimizes this effect.”
@ lucy.sierracircuits
Thanks for the quick reply, but I know very well that there will always be parasitic inductances and capacitances associated with the probe tips and connections that will load the signal, but that was not the point of my question. Maybe my question was misunderstood!
So here it is, I know that there are techniques and/or recommendations for positioning Test Point Pads so that they affect the signal integrity as “least as possible”, and this is the subject that particularly interests me. How to place these Test Point Pads on different types of signals without degrading their integrity; on high-speed networks, on I2C, SPI, UART networks, on high-current networks, on Kelvin connections, on RF networks, etc. What is the best technique to route them for each type of signal?
Thank you 
Ok, let me do some more digging.
https://youtu.be/ZYUYOXmo9UU?si=eqHSrRN9nQxv0Sq7&t=1h42h24m gives you a direct answer. Provided you make your layout with lumped elements. If you have some long traces connecting two lumped elements groups, you are not putting test points along those traces anyway, that would be useless. All tests points are lumped within each group on either side of the (longer) traces connecting them.
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Placing test points are critical for impedance RF lines. For lower frequency interfaces like UART, SPI, I2C test point placements are not that critical. For Kelvin connection place the test points close to the reading point of IC and keep the routing of both the lines symmetrical and equal length. Test point sizes should be as small as possible. For RF impedance lines adding test points mean affecting the impedance of the line resulting in reflections and distortions in signal. There are few things to look at such as the stub length. If the test point is not placed in the same line of communication but as an extension then stub length should be calculated and make sure the test point is placed well within the limit. Test point can be placed in the line of communication but due to change in size impedance of the line will change. Keep the test point size as less as possible. Place the tests points always towards the receiver end. If possible even vias can be used as test points by opening their soldermask. Vias are small and is generally used for completing the connections that way the impedance also would not change much and stub length is also avoided.
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Thank you for your answers but I am looking more for a kind of “Technical Guide” that would explain the best techniques for placing test point pads for each type of signal, with concrete examples, and that I could provide to our layout team as a reference.
Since it does not seem to exist, I will probably write one with my personal knowledge and by gleaning information from the reference sites that I know.
However, if anyone ever finds one, do not hesitate to publish it here.
Thank you all for your participation and efforts.
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We don’t have any technical guide on this topic, unfortunately. If you do write one, let me know, I’d be happy to help you promote it.
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I do not think you will find a single document that will provide you with what you are asking for. Reason is that there are too many variables to cover for every type of signal. Many high speed signal levels are too sensitive to see with common test gear and most test gear will swamp/detune the signal the moment that you attempt to touch the probe to the circuit. In some of those cases, you are out of luck or might get by with some type of capacitive pickup probe (I remember making a few rough versions years ago with varying levels of usefulness).
Then there is the whole mechanics of probing. If you are thinking bed-of-nails fixture? If so, then probes are grouped into size ranges that specify minimum pitch and maximum height to reach around component bodies. Taller components increase the adjacent distance to probe locations.
Some ICT fixtures are meant more as a method to read net localized shorts, resistance, or capacitance. Some ICT routines may attempt to inject code or waveforems in order to look for a particular outcome from a circuit instead of viewing real life operation signals.
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