I am designing a PCB with multiple high current traces; can I route them through a single via or should I use multiple vias?
Multiple vias absolutely.
Multiple vias are better, though the difference may not be very big. But it is possible to quantify this to some degree. To begin with let’s consider the case for a single via solution. What I shall say assumes that the via plating thickness is about the same as the copper foil thicknesses that you are linking together (for 18um / 0.5oz and 35um / 1oz laminates this is a fair assumption, otherwise apply scaling factors).
Suppose you have worked out that the high current trace requires a width of 3mm, then a drill circumference of 3mm (very roughly a 1mm drill) will give the via equivalent current handling capacity to the trace. An alternative could be two vias of 0.5mm drill diameter.
The obvious objection that may be raised is one of heat build-up, but the reality is that in a still-air environment, the thermal conductivity of the PCB materials (by this, I refer to the core or prepreg material, not any copper layers) is better than that of air. So the result is that the via is generally able to handle the current with a lower temperature rise than the traces that it connects. Of course, in a forced air environment where you are depending on fans, this changes a little. However, the difference may not be as much as you might think, but now you have to take into account the thickness of the PCB and it gets a lot more complicated.
As mentioned earlier, if you are using thicker copper layers, you need to adjust the number of vias accordingly. So a 70um / 2oz thickness and you would be best to double the number of vias, and for 100um / 3oz use triple the number. This assumes the vias are only plated to an equivalent thickness of 35um or so.
Final remark, what about filled vias? As has already been said, the thermal conductivity of the FR4 (or whatever) is better than the air, including the air in the via; so this factor does not matter much. If you want you can solid copper fill and cap the vias (e.g. type 7 capping process), but the gain is not much.
The question of whether to use one big via or several smaller ones may come down to reliability, where a failure of one smaller via in an array will be less visible than if everything depended on the integrity of one larger via. But with PCB manufacturing today, the risk is small anyway.
Some of this might sound a little bit contradictory to general schools of thought, but the hard data is out there on the net for the want of looking for it.
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Thanks a lot, Jonathan, for the detailed explanation.
This is helpful. Thanks, Jonathan.