Best Practices for Handling High Currents on PCBs

Manufacturing
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We need to handle high currents on a PCB, approximately 30 Amps sustained, which necessitates using higher copper thickness. Up until now, we have only used 35 microns (1 oz) in our designs, so for us, ‘high thickness’ means 70 microns (2 oz) or 105 microns (3 oz).

We are seeking advice on the considerations and best practices for working with thicker copper. Since this is a broad topic, here are some specific questions:

  • Many manufacturing houses seem to cap at 105 microns. Is this typically the maximum, or are higher thicknesses available?
  • Can the copper thickness in the inner layers match that of the top and bottom layers?
  • When routing high currents through multiple board layers, is it necessary or preferred to distribute the current equally across the layers? Is this even possible?
  • Regarding IPC rules on trace widths: Do these guidelines hold true in practical applications? For instance, for 30 Amps and a 10-degree temperature rise, the graphs suggest a trace width of about 11mm on the top or bottom layer.
  • When connecting multiple layers of high current traces, what is the best practice? Should we place an array or grid of vias near the current source, or should the vias be distributed throughout the high current trace?

We would greatly appreciate any insights or experiences you can share on these matters.

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Some fab shops can provide much higher copper weights (like 10 oz or more and also can be selective on portions of the artwork). I have never gone to that level but I have done 4oz finished on top/bottom as well as multiple layers with 2 oz on all layers. You should choose a fab and discuss what they can support. Keep in mind that thicker copper also requires larger minimum track widths/spacing requirements.

I will warn you that if you choose to parallel layers to increase copper capacity, you do need to properly connect them with multiple vias. That said, be careful about too many pattern vias as more vias might help with current transfer between layers, but those same vias can create current restrictions for current that is intended to pass across the layer surface (think hole = increased resistance = increased heat).

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We can plate up to 7oz copper but line and space needs to be at least 24mil. Would need to see the design and stack-up but inner layers can have heavy copper as well. Problem is having enough resin to get proper fill around high traces and not have topography issues. There are materials, basically liquid dielectrics, that are designed to be used as a pre-fill that address this problem.

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Isola has supplied up to 12 ounce copper on our 370HR material. The most critical concern from a materials perspective is adequate fill without glass stop. Woven e-glass has a lower dielectric break down strength compared to the resin system. Also, a newer resin system like IS550H is designed for and is better suited for high voltage, high current and high heat. This material was designed as alternative to fill the gap between FR-4 and ceramic materials at a better cost to performance ratio initially for the automotive industry.

Make sure the PCB fabricator you use has the design knowledge and experience to process heavy copper materials.

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When routing “parallel” conductors for high current paths it would be idea I suppose to have them identical, but in practice it’s pretty much impossible. For example, the inner layers are set up with a copper thickness (most often ½ oz.) whereas the outer layers can be plated up to 3 or 4 ounces. As far as I know, the IPC graphs are as valid as any other. Calculating the “correct” current flow has created many tables and graphs and more than one disagreement ever since Onderdonk started this whole mess.

Lastly, I would say if you have to high current traces of the same net running on top of one another, or even ground pours over ground planes, keeping those “stitching traces” can be helpful for several reasons, in this case helping to keep the current flow as balanced as possible.

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Who’s Onderdonk?

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Up until about 10 years ago, when PCB designers searched for information about the current needed to melt a trace on their boards, only two names popped up in the literature, W. H. (Sir William Henry) Preece and I. M. Onderdonk. Each is credited with developing a unique equation, bearing their respective name, and those equations became the basis for many PCB calculations.

Preece’s background is considerably well known. In the 1880s, he was a consulting engineer for the British General Post Office and became engineer-in-chief in 1892. At that time, the Post Office was responsible for the telegraph (and later wireless telegraph) system in England. He published three papers in the Proceedings of the Royal Society of London in the 1880s that formed the basis for his famous equation1

On the other hand, almost nothing is known about Onderdonk. (The author) found no earlier reference than a small article in a 1928 issue of the General Electric Review by E. R. Stauffacher.3 Onderdonk’s equation is referenced a few places in the literature, and it is always quoted as a “given” (much like we take Ohm’s law as a given.) (and) found no original work by Onderdonk.

The above is from PC Design Magazine.

And I personally never found a worse or more boring writer than Onderdonk. I therefore invoke his name when I need a demon.

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As there are already some good answers to the questions raised, here are a few more things that might turn out to be important.

Connecting multiple layers with high current traces - if you have the choice between a few larger diameter vias or many tiny vias, choose the larger diameter vias. This is because they delocalise the heat better than the small ones.

Concerning vias, you will need to check with the PCB manufacturer what copper thickness they will be plated up to. It may be rather thinner than the trace thickness, and if so, you need to allow for this.

Still concerning vias, if the via plating thickness is the same as the trace thickness, and the via internal circumference is the same as the trace width (ok, this will not be true, but follow the thinking here), then the via temperature rise will be less than the trace temperature rise since the PCB materials all have a higher thermal conductivity than the air does which is present on the outer layer conductors. This principle can guide you in choosing how many vias and what size they need to be.

As the frequency of operation is not stated, it is assumed to be DC. If this is not the case, you need to allow for skin effect. This matters for high power converters operating at frequencies that might not seem to be all that high. For this analysis, you can ignore the DC component; it is only the AC that matters.

Board assembly: make sure that those who assemble your board know about the thickness of the copper on your board. There comes a point where the normal convection ovens with their direct heating approach may not get the heat into the joints fast enough to get reliable solder joints. In situations like this vapour phase is a much better technology.

Once soldered, rework will be very hard to do. Make sure your design simulations work as expected since getting a “second chance” by modifying the prototypes may not be possible.

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If only a few of your traces need to handle 30A, I recommend soldering a copper wire on top of the trace. This approach is often more cost-effective than using specialized materials like 100μm copper. A 2mm² copper wire is inexpensive and provides far greater durability than a thin PCB trace.

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Certainly, you can go beyond 105 microns for inner layers, but there are several factors to consider. A PCB is fundamentally a stack-up of epoxy, copper, and glass fiber, so you can theoretically adjust the thickness of the inner layers. However, thicker inner layers are less effective at dissipating heat due to the poor thermal conductivity of the surrounding epoxy.

From my experience, we worked on a design that required handling 16A across several traces. We chose to use 4mm traces on both the top and bottom layers and employed large-diameter vias along the entire length of the trace. This approach allowed us to manage the high current without relying on inner layers, where heat dissipation would have been less efficient.

In general, if you’re considering using thicker copper for high-current applications, it’s crucial to consult with your PCB fabricator early in the design process. They can provide guidance on what copper thicknesses they can reliably support and what design adjustments might be needed to handle heat dissipation effectively. Additionally, using techniques such as placing a grid of vias or opting for larger diameter vias can help manage current distribution and minimize heat buildup.

Keep in mind that while IPC guidelines for trace widths provide a good starting point, they are based on ideal conditions and might need adjustment based on your specific design and environmental conditions.

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The most reliable source for addressing your questions is the PCB vendor you choose. PCB manufacturers often specialize in different areas—some excel with high-speed, tight-tolerance designs, while others are better suited for high-power applications. Although most vendors can accommodate various requirements, those outside their specialty may come with a price premium.
If your high-current design also involves high voltages, remember that you may need to address additional creepage and clearance requirements to comply with safety standards. Early discussions with your vendor can ensure your design is both feasible and optimized for the best performance.

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One key consideration is that while PCB manufacturers can often fabricate both tight trace/gap widths and thicker copper (e.g., 1 oz, 2 oz, 3 oz), they typically can’t achieve both on the same board without wider trace spacing. When using thicker copper, plan for greater trace spacing than on standard PCBs.

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You might consider contacting a PCB fab directly about thicker copper options, but be sure to ask about any additional costs involved. Even if a fabricator can produce thicker copper, the associated cost increase may impact your decision.

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Regarding copper thickness distribution, it’s worth noting that the copper on outer layers is typically thicker than on the inner layers. Fabricators start with a standard copper-clad thickness (e.g., 17.5 or 35 µm) for inner layers, then etch and bond them together. After drilling, the PCB goes into a plating bath, which increases the copper thickness on the outer layers and in the vias. This process results in uniform inner layer thickness, with thicker outer layers.

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For high currents, keep traces wide and as short as possible to minimize resistance and reduce I²R heating. If you’re using parallel traces on different layers, avoid narrowing any part of either trace, as this will increase resistance and generate excess heat.

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In terms of via placement, clustering vias near the current source tends to minimize net resistance, offering better performance for high-current applications. As for asymmetrical copper weights across layers, modern fabs can handle unbalanced designs if needed, though standard configurations (thicker outer layers, consistent internal thicknesses) are often sufficient for most applications.

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For manufacturing thicker copper, keep in mind that while some fabrication houses offer up to 3 oz, the availability of higher thicknesses (like 4 oz or more) is limited, which may restrict vendor options and potentially add lead time since not all board houses stock above 3 oz copper materials.

Regarding copper thickness on inner layers, typically, outer layers are thicker due to plating during manufacturing, especially if the board includes SMD components. If aiming for 3 oz, plan for it on specific layers as fabricators can maintain standard thicknesses on inner layers.

For high currents across layers, distributing current equally is preferable and achievable by ensuring uniform copper patterns across all layers, with connections made at both the source and destination. Employ a grid of vias, or a single large plated through-hole, to minimize hotspots and help balance the current load effectively.

When using IPC trace width guidelines, I’ve found them reliable. However, if running high current on multiple layers, consider adding extra copper to offset any compounded temperature rise. Also, calculate trace resistance and wattage, either using an online tool or estimating based on copper thickness. This helps anticipate heat dissipation needs beyond just the copper layers—accounting for connectors and other components, which are crucial in high-current scenarios.

For vias in high-current traces, the best placement depends on whether your source and destination are surface mount (SMD) or through-hole. With through-hole components, the plated hole connects all layers, so extra vias might not be needed. For SMD pads, place vias close to the source and destination, ideally filled vias directly in the pad. This ensures current flows across multiple layers from the start, rather than staying on a single layer until reaching the first via. Positioning vias farther from source and destination means less efficient current distribution, as more current flows through the initial vias, potentially causing them to overheat. This approach may also require more vias and take up valuable routing space, possibly increasing board size.

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For high-current PCB design, here are some pointers based on my experience:

  1. Copper thickness: Many manufacturers cap at 105 microns (3 oz), though higher thicknesses may be available with trade-offs in board tolerance, cost, and production time. For internal layers, copper can be plated up, but heat dissipation is less efficient than on outer layers.
  2. Inner layer copper: Yes, inner layers can match outer thickness, but they often work better with impedance-controlled striplines. Microstrips on outer layers are easier to adjust for impedance post-lamination, unlike internal layers.
  3. Current distribution across layers: It’s preferred but challenging to balance current across layers. Typically, this is managed with ground planes using stitching vias, which help even out current but may add complexity to routing.
  4. IPC trace width guidelines: The IPC-2152 standard is reliable for current capacity but doesn’t factor in nearby heat-generating traces or skin effect at higher frequencies (e.g., 1 MHz and up). Be sure to check acceptable voltage drops alongside width guidelines.
  5. Via placement for high-current traces: Distribute vias along the trace rather than clustering near the source. Avoid placing same-direction vias too close to prevent mutual inductance, which can increase total via inductance. A general rule is to space them at least a board thickness apart.

Lastly, maintain symmetric stackup to prevent warpage; some fabricators can manage asymmetry but at higher costs and longer lead times.

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Wait … are you saying that it is common to adjust trace size (or maybe just cover-layer thickness?) even after lamination, in order to get a more precisely controlled impedance?

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We don’t do it a lot, but yes traces can be tweaked a little (mostly to increase Z) post lamination, and that usually we try just to manipulate the solder mask if we can. With all these newer mask types I think there’s many more choices/methods.

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