Best Practices for Handling High Currents on PCBs

We need to handle high currents on a PCB, approximately 30 Amps sustained, which necessitates using higher copper thickness. Up until now, we have only used 35 microns (1 oz) in our designs, so for us, ‘high thickness’ means 70 microns (2 oz) or 105 microns (3 oz).

We are seeking advice on the considerations and best practices for working with thicker copper. Since this is a broad topic, here are some specific questions:

  • Many manufacturing houses seem to cap at 105 microns. Is this typically the maximum, or are higher thicknesses available?
  • Can the copper thickness in the inner layers match that of the top and bottom layers?
  • When routing high currents through multiple board layers, is it necessary or preferred to distribute the current equally across the layers? Is this even possible?
  • Regarding IPC rules on trace widths: Do these guidelines hold true in practical applications? For instance, for 30 Amps and a 10-degree temperature rise, the graphs suggest a trace width of about 11mm on the top or bottom layer.
  • When connecting multiple layers of high current traces, what is the best practice? Should we place an array or grid of vias near the current source, or should the vias be distributed throughout the high current trace?

We would greatly appreciate any insights or experiences you can share on these matters.

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Some fab shops can provide much higher copper weights (like 10 oz or more and also can be selective on portions of the artwork). I have never gone to that level but I have done 4oz finished on top/bottom as well as multiple layers with 2 oz on all layers. You should choose a fab and discuss what they can support. Keep in mind that thicker copper also requires larger minimum track widths/spacing requirements.

I will warn you that if you choose to parallel layers to increase copper capacity, you do need to properly connect them with multiple vias. That said, be careful about too many pattern vias as more vias might help with current transfer between layers, but those same vias can create current restrictions for current that is intended to pass across the layer surface (think hole = increased resistance = increased heat).

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We can plate up to 7oz copper but line and space needs to be at least 24mil. Would need to see the design and stack-up but inner layers can have heavy copper as well. Problem is having enough resin to get proper fill around high traces and not have topography issues. There are materials, basically liquid dielectrics, that are designed to be used as a pre-fill that address this problem.

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Isola has supplied up to 12 ounce copper on our 370HR material. The most critical concern from a materials perspective is adequate fill without glass stop. Woven e-glass has a lower dielectric break down strength compared to the resin system. Also, a newer resin system like IS550H is designed for and is better suited for high voltage, high current and high heat. This material was designed as alternative to fill the gap between FR-4 and ceramic materials at a better cost to performance ratio initially for the automotive industry.

Make sure the PCB fabricator you use has the design knowledge and experience to process heavy copper materials.

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When routing “parallel” conductors for high current paths it would be idea I suppose to have them identical, but in practice it’s pretty much impossible. For example, the inner layers are set up with a copper thickness (most often ½ oz.) whereas the outer layers can be plated up to 3 or 4 ounces. As far as I know, the IPC graphs are as valid as any other. Calculating the “correct” current flow has created many tables and graphs and more than one disagreement ever since Onderdonk started this whole mess.

Lastly, I would say if you have to high current traces of the same net running on top of one another, or even ground pours over ground planes, keeping those “stitching traces” can be helpful for several reasons, in this case helping to keep the current flow as balanced as possible.

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Who’s Onderdonk?

Up until about 10 years ago, when PCB designers searched for information about the current needed to melt a trace on their boards, only two names popped up in the literature, W. H. (Sir William Henry) Preece and I. M. Onderdonk. Each is credited with developing a unique equation, bearing their respective name, and those equations became the basis for many PCB calculations.

Preece’s background is considerably well known. In the 1880s, he was a consulting engineer for the British General Post Office and became engineer-in-chief in 1892. At that time, the Post Office was responsible for the telegraph (and later wireless telegraph) system in England. He published three papers in the Proceedings of the Royal Society of London in the 1880s that formed the basis for his famous equation1

On the other hand, almost nothing is known about Onderdonk. (The author) found no earlier reference than a small article in a 1928 issue of the General Electric Review by E. R. Stauffacher.3 Onderdonk’s equation is referenced a few places in the literature, and it is always quoted as a “given” (much like we take Ohm’s law as a given.) (and) found no original work by Onderdonk.

The above is from PC Design Magazine.

And I personally never found a worse or more boring writer than Onderdonk. I therefore invoke his name when I need a demon.

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As there are already some good answers to the questions raised, here are a few more things that might turn out to be important.

Connecting multiple layers with high current traces - if you have the choice between a few larger diameter vias or many tiny vias, choose the larger diameter vias. This is because they delocalise the heat better than the small ones.

Concerning vias, you will need to check with the PCB manufacturer what copper thickness they will be plated up to. It may be rather thinner than the trace thickness, and if so, you need to allow for this.

Still concerning vias, if the via plating thickness is the same as the trace thickness, and the via internal circumference is the same as the trace width (ok, this will not be true, but follow the thinking here), then the via temperature rise will be less than the trace temperature rise since the PCB materials all have a higher thermal conductivity than the air does which is present on the outer layer conductors. This principle can guide you in choosing how many vias and what size they need to be.

As the frequency of operation is not stated, it is assumed to be DC. If this is not the case, you need to allow for skin effect. This matters for high power converters operating at frequencies that might not seem to be all that high. For this analysis, you can ignore the DC component; it is only the AC that matters.

Board assembly: make sure that those who assemble your board know about the thickness of the copper on your board. There comes a point where the normal convection ovens with their direct heating approach may not get the heat into the joints fast enough to get reliable solder joints. In situations like this vapour phase is a much better technology.

Once soldered, rework will be very hard to do. Make sure your design simulations work as expected since getting a “second chance” by modifying the prototypes may not be possible.

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