Is it acceptable for PCB traces to cross on different layers?

Design and Layout
1

PCB traces carrying electrical signals generate electromagnetic fields, which can lead to inductive and capacitive crosstalk between adjacent traces. I’ve observed designs where signal traces cross each other on immediately adjacent layers without an interposed ground plane. My understanding is that this configuration could potentially cause signal coupling due to crosstalk, as the electromagnetic field from one trace might induce an unwanted signal in the crossing trace.

Given these considerations:

  1. Under what circumstances, if any, is it acceptable to have signal traces crossing on adjacent layers without a ground plane between them?

  2. Are there specific design rules or best practices for managing crosstalk in such situations?

  3. How do factors like signal frequency, trace length, or signal type (digital vs. analog) influence the decision to allow or avoid such crossings?

2

There are essentially two possible situations here. Say you have traces on layers 1 and 3 but have a ground plane between them. In this situation, there crossing is irrelevant with the exception that if they were both high-speed data lines then both their grounds would be in the same place which is probably not good. Now let’s take the ground plane out. If two traces cross each other (as opposed to running parallel) the effects are minimal, and unless at least one of them is a high speed data line, probably irrelevant. Passing some signal over a “chip select” or “reset” line is almost certainly unimportant. The length and frequency etc., are the same as for any other situation - shorter is better, larger spacing is better, slower is better, etc. No hard and fast numbers though.

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3

And don’t forget these 7 DFM guidelines for efficient PCB traces.

4

If the two signals cross at a 90 degree angle, there will be very little crosstalk, and it is almost always fine. The capacitance between the two lines is nearly zero, so energy from one line can’t couple into the other very effectively.

If the two signals are parallel, whether they are on the same or adjacent planes, then there can be trouble. The capacitance is (roughly) proportional to the area that the two conductors have facing each other, so the longer the parallel run the more ability for one signal to couple energy to the other. If either signal has high edge rates (dV/dt and di/dt), and the other has low noise margin, then there will be trouble. The best practice for avoiding the trouble is that any signal with high edge rates should be routed with a return path, unbroken all the way from source to sink. This is usually a ground plane, or wide ground trace running directly under the signal trace on an adjacent layer.

It’s not exactly the frequency that matters, it’s the edge rate. High-frequency signals require a high edge rate, so it’s easy to see that these signals need special care. But the low-frequency signals that have a high edge rate can put some noise on the parallel traces, thereby causing a glitch, and these can be difficult to troubleshoot because they happen less frequently.

Digital signals tend to have high edge rates, so they can often be the source of crosstalk. But analog signals can also be high-frequency, and cause crosstalk as well. Similarly, digital signals usually have good noise margin, so they’re not as susceptible to crosstalk as the analog signals. But again, today’s low-voltage digital devices may have less noise margin, and analog devices may have low impedance that helps their noise margin, so these are not absolute rules.

Almost always, signals with high edge rates need a good return path, to avoid SI (signal integrity) and EMI (electromagnetic interference) problems.

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5

Thanks for the very complete answer, Gerry. :slight_smile:
I don’t know if you’ve seen this but we’re hosting a LIVE Q&A: Stack-Up Design on Wednesday. In case you want to join.

6

Yes, I just signed up for that one. Thanks, Lucy.

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7

Signal traces essentially act as metal conductors, and when you have two separated traces, they function as capacitors due to the electric field between them. Increasing the proximity or the surface area between them increases this capacitance. While this can be advantageous in some designs, especially for high-frequency signals, designers aiming for low noise or specific frequency characteristics may prefer to avoid creating unintentional capacitance between different signal traces.

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8

It depends significantly on the speed and signal integrity requirements. The recommendation to have plane layers adjacent to your traces primarily ensures an uninterrupted return path beneath or above the traces.
For high-speed signals, especially those operating in the hundreds of MHz and beyond (such as DDR memory or gigabit Ethernet), breaking this return path by having other traces running below or above can lead to serious issues with EMI and signal integrity. The exact “crossover” frequency where this becomes significant isn’t universally defined, but for low-speed signals like I2C operating in the kHz to low MHz range, it’s generally less critical. However, for signals in the hundreds of MHz and beyond (such as DDR memory or gigabit ethernet), maintaining unbroken reference planes for the traces is highly advisable.

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9

It is generally acceptable for signals to cross on adjacent layers. However, if signals run close and parallel to each other on adjacent layers, there is an increased likelihood of cross-talk. Additionally, layer separation plays a crucial role. Typically, the stack-up should be designed so that each signal layer is close to a plane layer, as the signal will couple most strongly to that plane layer. Ensuring adequate separation between adjacent signal layers, where possible, can help mitigate potential issues.

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10

In our standard stackup for multilayer PCBs, especially those with 12, 14, or more layers, we typically arrange two routing layers next to each other, with a ground or power plane on either side. This pattern is consistently repeated throughout the stackup.

We designate one layer in each pair for routing signals in the X direction and the other for routing signals in the Y direction, ensuring that signal crossings occur at right angles. This minimizes, though doesn’t entirely eliminate, coupling between signals.

For signals running parallel on adjacent or even the same layers, we have strict design rules that limit the allowed length of parallelism. These rules vary based on the type of signal (such as clocks, resets, pull-ups) and the associated edge rates.

How are these design rules established

The process of establishing design rules is multi-step and somewhat dependent on the capabilities of your toolset. One of the first steps is to define the signal or net classes required for the design. For instance, class 1 signals are the most critical, like clocks, and we specify specific orthogonal routing layers (e.g., layers 6 and 7), spacing (e.g., 30 mils from other signals), and desired impedance (e.g., 50 ohms ± 10%) for these signals.

Class 4 might be reserved for power nets that don’t require a full plane, while class 8 might be for signal return (GND) planes that need a full layer or multiple layers.

Signal Classes

The naming of signal classes isn’t fixed—you can use numbers (e.g., Class 1, Class 2), letters (e.g., Class A, Class B), or even colors (e.g., Class Red, Class Blue). Once signal classes are defined, each signal in the schematic is assigned to a class using attributes. For instance, the signal’s name is one attribute, and its class is another.

During the layout and routing stage, the design tool uses these attributes to guide the routing process. Instructions will specify the order in which signal classes should be routed, such as “route all class 1 signals first,” followed by class 4, class 2, etc. However, the routing order isn’t strictly tied to the numerical or alphabetical sequence of the classes. It’s important to note that despite tool assistance, routing and layout still involve significant manual input; it’s not a fully automated process.

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