Originally published at: https://www.protoexpress.com/blog/ipc-class-2-vs-class-3-different-design-rules/
As circuit board manufacturers, designers often ask us about the difference between IPC Class 2 and Class 3. Class 1 does exist although we rarely produce boards that fall into this classification. Most of the time, even if the end-use of the product only requires Class 1, we will make it Class 2 just to ensure a better performance.
This post on class 3 design rules specifies a 3.54 mils minimum dielectric thickness (now 2.56 with 6012F), but IPC-6012 specifies this requirement applies only if the minimum dielectric spacing is not specified in the procurement documentation. So if I specify Class 3 on the fab drawing with a minimum dielectric spacing of X (say 2.3 mils) and Sierra agrees to manufacture it, I’m golden? Breakdown voltage on test coupons covers it? What IPC standard specifies what test coupons and tests must be applied to a Class 3 board?
Some of this has changed so will have better answer on Monday. The short answer for now is if a customer sends us a Class 3 job, we would review and make sure it meets all the requirements. We wouldn’t accept your data and call it good. Our CAM scripting automatically generates all the test coupons when Class 3 is specified.
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“make sure it meets all the requirements”: that’s my point, what is the requirement for dielectric thickness? Fab shops are typically quoting the 3.54 mils (now 2.56 with 6012F), but the standard only requires that if the minimum dielectric spacing is not specified in the procurement documentation. Sounds like a loophole in the standard.
Finally got a good answer on this. The standard was 3.54 mils. It can now go down to 2.56 mils as long as the specification drawing is dated after 1/1/2024. These are default minimums that must be met. If the procurement documentation calls for something less it will not meet Class 3 and would need to be questioned. There isn’t a loophole.
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