Ask Me Anything with Mike Jouppi

Have a question on thermal management? Post in this thread before April 10th and Mike Jouppi will answer!

Let me ask the first question: What are the key considerations when designing thermal management solutions for high-power density PCBs, and how do you ensure optimal heat dissipation while maintaining reliability and performance?

I would get as much information from the electrical design engineer (EE) regarding the power dissipations as early as possible. This would include components, traces, connectors and any other power sources. If I didn’t already know, I would assume my worst case boundary conditions for a preliminary thermal analysis. I would work with the board designer, if that was not the EE, to determine a preliminary board stackup and layout. I would then run a preliminary thermal analysis to determine where our hot spots are early in the design, so that we could start designing around our problem areas. Details regarding component thermal resistances are also considered in the prelimiary design.

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My boards are usually eight to twelve layers. Are there stack ups that are more thermally efficient? If so, what are they?

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Mike! Hello my old friend! How are you? Say – I’ve got a question about heavy copper and the recommendations of IPC-2221 and 2152. Can you tell us the story of how you discovered the flaws in 2221, the digging you did in the Library of Congress, and how that came to form IPC-2152?


I try to get as much copper near the components as possible. You have to balance your stackup, so that would push the same to both sides. Keep in mind that copper is roughly 1000 time more thermally conductive than the dielectric. The shorter the path to the copper the better. Once the energy hits the copper it will spread and minimize the temperature rise from a given heat source.


Hello Mark, I will try to keep it short. I don’t call issues in the design standards as flaws. I simply describe the data for what it is. The design community, which is all of us, are responsible for updating and changing what we design to. I think more should be done, but I’m a minority.

In 1999, I wrote to the US Navy looking for the data that went into the charts you find in IPC-2221. The Navy pointed me the National Archives where I found reports from the National Bureau of Standards documenting the testing performed in the 1950’s. That data was for external conductors only and the curves were created from a mix of test data and test boards. There were boards of varying thickness, some had a copper plane on the back and some didn’t. The board materials were XXXP and epoxy.

IPC-2152 charts represent trace heating in a 0.07-in thick, polyimide board. We tested following IPC-TM-650, and found that there was a small variance in temperature rise, for a given cross-sectional area, for different weights of copper, 1/2oz, 1oz, 2oz and 3oz. Thinner coppers, for the same cross sectional area, have less temperature rise than thicker. Internal run a little cooler than external in air and they run about the same in a vacuum. We, IPC task group 1-10b, were working toward characterizing the relationship between traces and the distance to copper planes. We had a dozen or more tasks that were still on the list of things to do when I left.

The kicker is that both IPC-2221 and IPC-2152 design charts represent a test board suspended in air. IPC-2152 vacuum data is for a suspended board in vacuum. The test boards are basically isolated traces in dielectric only. It is hard to describe the IPC-2221 data without having it in front of you.

The temperature rise of a trace in a multi-layered board with copper planes is much lower than what the charts tell you. The temperature rise is lowered again when the mounting configuration (wedge lock, or bolted) is taken into consideration.

IPC 2221 and 2152 are, for the majority of cases, conservative for estimating temperature rise as function of current and trace size. They just don’t give you a very good estimate for the actual temperature rise that will occur in any design. I also believe people don’t have a good way of managing parallel conductors. This is why I promote modeling the trace power in as fine a detail as possible for high current applications.


Hi Mike. Would you care to share cooling strategies you have used or seen in aerospace designs?

hello Mike! I was wondering if it’s possible to manage MOSFET heat dissipation without any heatsinks?

Have you used heavy copper traces and layers in your designs to dissipate heat for space applications. What do you recommend? (2 to 3oz?)

I often design power modules and I’m curious if there’s a set rule for cooling SMD devices properly. Some place heatsinks on the bottom, others put them on top directly over SMD components with plastic packages.

Many power ICs and MOSFETs have large thermal pads on the bottom which seems like it should transfer heat well downward. But adding about 2mm of FR4 PCB material can act as a thermal insulator. And compared to the epoxy resin layer on IO packages, which is usually 1mm or less, it doesn’t seem like it could be worse.

And don’t forget that some power ICs don’t even have proper thermal pads!

So my question is what’s the better approach? Putting the heatsink on the bottom or on top? Does copper thickness play a role?

Is there an optimal thermal via size, spacing, and layout for linear voltage regulators on one side of a multi-layer PCB?

Also, semiconductor datasheets provide thermal info based on standard PCB dimensions and copper configuration. What is the best way to equate a new design to this information in terms of copper weight (or thickness), area and dielectric thickness?

Strategies for PCBs…
As soon as possible I run a preliminary thermal analysis (computer models and or hand calculations) and look at where my hot spots are based on power dissipation estimates for components, traces, connectors, etc. I start with conduction only. I look at all of my heat transfer paths, but don’t add convection or radiation unless necessary. Then each hot spot, what ever it may be, becomes the focus of how to manage it’s temperatrure. I increase copper thickness and/or add layers to get the temperature rise on the board to an acceptable temperature.
I would work with the board designer to enhance conduction paths from the hot spots to mounting points. We would use thermal vias to increase the conduction path from hot components to copper planes, as well as the planes to the mounting surface.
Managing high current and high current pulses are evaluated and the power is used in the preliminary thermal analysis. I would assess high current pulses by assuming the temperature rise is contained in the trace with not heat transfer path out, then add material around it if necessary.

I get a strong understanding of the heat transfer through mounting interfaces, wedge locks, bolted interfaces, etc. What I mean by this is that I look at the materials, surface roughness, clamping forces and then calculate the interface heat transfer coefficient between the surfaces. This helps in understanding where the bottle necks are in the heat transfer path from hot spots to the mounting surface, which it typically where the majority of energy has to be transferred.

I’ve seen people incorporate heat pipes, thermoelectrics, wax, copper slugs, metal cores, copper heat sinks, full pcb aluminum housings and more. There are always solutions.


hello Mike! I was wondering if it’s possible to manage MOSFET heat dissipation without any heatsinks?

It depends on how you want to define heatsinks and how much power you have to manage. In a preliminary thermal analysis I would have an estimate of the board temperature where that MOSFET is and then based on the packaging thermal resistances I would assess what is needed to keep the junction temp within limits.


My first step, to get early board temperarture estimates where I need them, is adding copper thickness and layers. I didn’t have to use 3oz very often. A lot of 2oz and copper fill. I also like to get copper layers as close to the source/top layers as possible.


Assuming I have already estimated the board temperature where the package is placed I look at the thermal resistances from junction to case and junction to board. Unless I have some air flow or I am attaching someting to the top of the package, the cavity down configuration is likely a higher thermal resistance to the board. The sink on the bottom makes me focus on getting the power to copper planes below the part using thermal vias and copper fill where I can. The thickness of the copper is key to your heat transfer path out away from the part.


I would make a spreadsheet that calculates the thermal resistance through a via at varying diameters and plating thicknesses. Then calculate multiple vias in parallel. You can create a set of curves that will help you assess size and plating thickness as a function of the number of vias you can get into an area. The goal is to minimize the thermal resistance.

I’ve seen component thermal resistance values based on JEDEC standard test methodologies, such as 2 layer and 4 layer. I like what they have done, but it requires a bit of study to look at the amount of copper in their stackup. I use the junction to case numbers and calculate the case to board thermal resistance myself. I would use the method that simulates your design the most.

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For some reason I couldn’t edit my other reply, so I’m adding more here. The optimal via size and plating in the vias will depend on the space you have around the voltage regulators. Typically, you have only so much board area to work with. Getting as much copper around the regulators as possible and connecting that copper to other layers that help spread the power into the board is the goal with the thermal vias. It is good to talk to your board manufacturer to see what their capabilities are for plating thermal vias. I’ve talked to some manufacturers that have controlled their plating to the extent that they can plate vias shut. The concern has been trapping chemistry in the vias in the past, but it is a good question to discuss with your manufacturer.

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Hello! Any recommendations for good resources on learning thermal management? Any software, learning materials, or particular topics you find helpful as a starting point?

Our small company typically works with low power DC (rarely more than 5V/1-2A), but we recently had a project jump to 12-24V, 10-15A. As a new(ish) grad (3-4 years out from BSEE), it felt like trial by fire (almost literally at times) just getting the board to function. Would love to hear what you recommend for someone interested in expanding their knowledge of thermal management with almost no experience.

Hi Mike! Can you share what components are most sensitive to thermal expansion and damage in the baking process? That might be a question for Sierra. Whoever can answer.