My first day as an intern, I was given a stack of books, told to read them and ask questions. I still remember Principles of Heat Transfer, by Frank Kreith as one of them. I also like Cooling Techniques for Electronic Equipment by David Steinberg. Fundamentals of Heat and Mass Transfer by Frank Incropera and David DeWitt, this has excellent convection correlations.
Get comfortable running some hand calcs in spreadsheets, study the topic and get a thermal analysis software tool.
I have been using Solaria PCB for doing the most recent work. Solaria is the main tool and runs around $5,000.00 for a forever license and and additional $5000.00 for the tool Solaria PCB. Solaria PCB will read in an ODB++ file and you get all the traces, vias, components, etc. I
I’ve also used Ansys ICEPAK, which I just googled if correct, was showing $22,000.00 for a perpetual license. I’ve used others as well. The hard part is taking the time to evaluate them to make sure they are doing what you want. Starting out makes this even more difficult, because it seems all codes have some issues to work around.
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That would fall more into thermal stresses. You have to look into the Coefficient of Thermal Expansion (CTE) for the parts and compare them.
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Hi Mike! Have a few questions:
Q1. Might you know of any open-source thermal simulation tools?
Q2. What might your design guideline be for how much temperature rise to allow for PCB copper traces? Something like 10’C to 20’C above the ambient temperature? What would be the absolute max temperature you would limit the PCB traces/copper pours to? 50’C, 60’C, 70’C?
Q3. Some power integrity tools will show the current density profile flowing through a PCB trace, via, copper pour etc. Might you have a design guideline for the max current density to allow for any area of a trace or via?
Q4. There are several formula’s out there for estimating the minimum PCB trace width that can handle a specified maximum current. Some of these formulas come from IPC standards. Which formulas are more reliable? Would you consider their estimates as conservative? What should we look for in the many online calculators that perform this task?
Q5. What would your guideline be regarding the current carrying capability of a via? Is there a formula for this? In a design, how much would you derate the current through the via?
Thank you.
Ernest
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Hi Ernest,
A1. Georgia Tech University is supposed to have archived a finite difference code called Systems Numerical Differencing Analyzer (SINDA). I’ve tried reaching them in the past, but never had any luck. Other than that I am not aware of any open source code. SINDA is written in FORTRAN.
A2. I recommend minimizing the temperature rise. Designers have used 10C and 20C when using the internal chart in IPC-2221 and IPC-2152. In either case you will likely not get the temperature rise you are thinking and it will likely be lower. I do not recommend sizing to those temperature delta’s if you had charts that represent your actual board. Parallel conductors are difficult to manage in a high layer count board. I recommend assessing your design and budget a set amount of power that can be associated with the traces in the board.
I would assess the maximum temperature of the traces based on the maximum temperature of the board and is acceptable for my components.
A3. I was working on that with the IPC task group 1-10b and the development of IPC-2152, but did not complete that. I was getting close by looking at power density.
A4. The equations represent a curve fit to the design charts. It’s important to understand what those curves represent. The boards are different than what you may think. It’s too hard to go into all the details here. Reliable is a tough term when referring to these charts. The IPC-2152 charts are the only set that you could build a board and recreate the same temperatrures for a given current and trace size. The charts in IPC-2221 are a hodge podge of data sets combined and there never was internal data, they just used half the current from the external trace chart to create the internal IPC-2221 trace chart, which was first a Military Standard. In almost all cases, the charts are conservative. Thin small boards may be an exception if there are no power or ground planes.
A5. I wasn’t able to get funding to investigate vias. I’ve calculated the cross sectional area of the barrel and treated it like a trace. The temperature rise is still a mystery, which will be determined by what the via is attached to and how much copper is around it. A copper plane or a trace that is larger than the cross sectional area of the via will act as a sink and help cool the via. A company in China did a excellent study on current carrying capacity in vias and via structures. I didn’t have any resources to do that work. If you can size a via using the cross sectional area defined for internal conductors from IPC-2152, you are already derated significantly with respect to temperature rise.
Q6. Who is responsible for creating PCB design standards?
A6. All of us, there is not government agency that does any of this type of work any more. IPC took this over for PCB’s and uses volunteers to advance our understanding. At this time there is no one in IPC that has any desire to advance the knowledge base around trace heating.
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Thanks a lot @mjouppi.tmllc for doing this AMA with us!
Everyone, thanks for your questions and here’s a little video of Mike discussing the design charts in IPC-2221 and IPC-2152.
And here is the file: https://pages.protoexpress.com/rs/727-TSC-367/images/How much different can your PCB be by Mike Jouppi.pdf?version=0
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Thanks Mike! Very insightful. Greatly appreciated.
Thanks, Mike! Love your YouTube videos btw.