We often see placement issues with decoupling capacitors during layout and DFM reviews, especially on high-speed and dense boards. I wanted to start a discussion on how designers approach decap placement to avoid power integrity and noise problems.
Decoupling capacitors act as local energy reservoirs, stabilizing voltage and suppressing transient noise caused by switching devices.
Poor placement can lead to voltage drops, signal integrity issues, and even EMI failures. The effectiveness of a decoupling capacitor is not just about its value. It’s heavily dependent on placement and loop inductance.
2 Likes
From a layout standpoint, the most important rule is:
Place decoupling capacitors as close as possible to the IC power pins
- Minimize the current loop area between the IC, the capacitor, and the ground
- Avoid long traces. Even a small inductance can cause voltage dips at high frequencies
- Place vias directly at or inside capacitor pads where possible
- Avoid routing traces between the capacitor and its via connection
For high-speed designs:
-
Use multiple decaps of the same value near the power supply. If not possible, add the lowest-value capacitor closest to the power supply.
-
Add bulk capacitors (e.g., 10 µF or higher) near the power entry
The goal is to create a low-impedance path for transient current.
1 Like
Placement strategy also depends on your stack-up and power plane configuration:
- Closely spaced power/ground planes:
Placement is slightly less critical since planes provide low inductance, but capacitors should still be within an effective distance of the IC
- Widely spaced planes or no planes:
Placement becomes critical, capacitors must be very close to the IC pins to compensate for the higher impedance
- For BGAs and dense layouts:
- Use via-in-pad or adjacent vias to minimize inductance
- Place capacitors under or around the BGA when possible
Also, prioritize:
- Smaller packages (0402/0201) for lower ESL
- Proper orientation to align with current flow paths
The optimal placement varies with switching speed, stack-up, and PDN design. But in most cases, inductance, not capacitance, is the limiting factor, so layout quality matters more than just capacitor value.
For a detailed breakdown of placement strategies across different stack-ups and design scenarios. See: Decoupling Capacitor Placement Guidelines Every PCB Designer Should Know.
2 Likes
