Differential Pair Width Calculation

I’m in the process of calculating the width of my 100Mb Fast Ethernet MDI differential pairs using TXLINE 2003 Microstrip software. I’m working with a 4-layer PCB, where the second layer is GND, the third is power, and the top and bottom layers are signal layers. While it’s clear how to calculate the distance for the top layer using the height parameter, I’m unsure about the bottom layer. Should I use the power layer or the GND layer as the reference for calculating the distance?
Additionally, I’ve heard that if the power layer is chosen as the reference layer for width calculation, it’s necessary to place 10nF capacitors between power and GND on both sides of the MDI differential pairs. Can you confirm if this information is accurate?

On a 4 layer with pwr plane on layer three, use layer three as the reference while routing on layer 4. Ethernet signals should be routed so that they have 100 ohm differential impedance. This can be achieved by using different stackups, but usually the layer with the differential traces will be adjacent to a ground plane layer to achieve the desired impedance. As far as the transformer goes, it depends on whether it is a discrete transformer, or integrated into an RJ45 jack. With discrete transformers it is recommended to separate the ground planes between each side of the transformer to prevent a path for noise coupling. It is also common to bridge the gap between grounds with several capacitors in case they are needed. It is not necessary or desired to have separate grounds when using an RJ45 jack with integrated magnetics which simplifies the design.

When routing a differential pair, it’s crucial to have a continuous ground plane underneath to control the capacitance between the traces and ground. One effective method is to use the top layer for signals and the second layer for the ground. This setup helps maintain controlled impedance.

In a microstrip design, the signal current flows on the signal plane, while the return current flows back on the ground plane below. This arrangement keeps impedance low, enabling the trace to function like a transmission line with minimal reflections and attenuation.

Avoid using a power plane as the basis for a microstrip because it interferes with the return current path, which should ideally be through the ground plane. Using a power plane in this setup requires stitching capacitors, each introducing about 10nH of parasitic inductance that can inhibit the return current. If you’re willing to accept increased inductance and slower rise times, you could consider this approach, but it’s generally not recommended for optimal signal integrity.

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