Have a question about DDR5? Post below and DesignCon speaker Xinran Li will reply!
What controlled impedance values would you recommend for DDR5 designs? Looking for insights on achieving optimal performance in DDR5 layouts. Any suggestions or best practices would be greatly appreciated!
What are the main differences between DDR4 and DDR5 in terms of layout and design considerations?
What tools or software do you recommend for simulating DDR5 signal integrity and ensuring optimal performance? Anything on a budget? 
Hi Xinran, Can you share tips or best practices for routing DDR5 memory traces to minimize signal noise and interference?
What are the key differences in power delivery requirements between DDR4 and DDR5? and what’s the impact on the design?
Has anyone encountered compatibility issues or interoperability challenges when integrating DDR5 modules with existing hardware or systems?
Are there any specific DDR5 layout guidelines or resources that you’ve found particularly helpful?
I actually have 2 questions:
- How do you approach thermal management and cooling considerations for DDR5?
- Are there any specific layout or routing techniques you’d recommend for high-speed DDR5 memory interfaces?
Hello Xinran! DDR5 seems hard…very hard…can you tell us what are some of the things you are seeing in the lab that you did not expect?
Hello! Here are some reference target impedance you can aim for:
DQ – 35 Ohm
Other SE signals – 50 Ohm
DQS – 70 Ohm Diff
DCK – 85 Ohm Diff
QCK – 50 Ohm Diff
For general routing insights, I highly recommend studying the JESD305 document from JEDEC. It contains a lot of good information on routing such as skew of different signals and between different signals. For example, skew between DQ bits should be within 1mm and skew between differential pairs should be within 0.1mm.
Another great material to look at is the DDR5 module design files from JEDEC. We call them raw cards. They are designed by the Micron, Samsung, or SK Hynix. These designs are all heavily simulated and is great to learn from.
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They are quite similar in many ways. Besides the two-subchannel topology and different signal configurations, the most important consideration is to make sure your design can accommodate the much higher data rates of DDR5. DCA bits are also double data rate for DDR5 RDIMM
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We work very closely with KeySight and have access to KeySight ADS, which has been extremely helpful us. Unfortunately we are not very aware of other DDR5 simulation solutions…
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Hi! Make sure the impedance are closely matched to the reference values I gave above. Try to avoid having too many vias on one trace. DDR is a parallel protocol so please also make sure trace length are tightly matched. There are also a ton of high speed signals to work with so plan out return paths. Check out JESD305 from JEDEC to understand these specs, they offered a lot of great advices in there. Like I responded above, the raw cards on JEDEC website are super helpful too!
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They are quite different as DDR5 module now takes in a 12V Vin_BULK and does DC-DC on module with a PMIC, rather than taking 1.2V VDD as input like DDR4. If you are making a DDR5 module, please make sure you read the PMIC specs and use the correct PMIC. There are many different DDR5 PMICs to choose from and they are all slightly different in many ways. I am not an expert in DDR5 power delivery but I do recall reading an interesting paper on the nuances of power plane impedance and signal skews. I will try to send it your way if I can find it.
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Usually, you can’t easily drop-in replace an existing system with older DDR with a DDR5 module.
But we found some very interesting issues within the DDR5 generation. Our product uses a DDR5 RCD as a “probe” on a RDIMM interposer to sniff the CA traffic between the controller and the module. The RCD on our interposer will be placed in a special mode called Validation Pass Through Mode. This mode essentially makes the RCD transparent to the system and we can get slowed down QCA signals from the back side to be analyzed by a logic analyzer. The problem we had is that the RCDs from different manufactures (Montage, Renesas, or Rambus) do not mix! There are some slight timing differences between them. If our interposer had a RCD from a different manufacture than the one on the DUT (device under test, the module that is being measured), the interposer will latch onto the signals incorrectly and we will decode corrupted data on the logic analyzer. This problem is still being looked into by us and some of the RCD vendors.
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JEDEC specs have been extremely helpful to us. Like I mentioned above, JESD305 is especially helpful for routing guidelines, and JEDEC module design files are great sources to learn from. But you do need to be a JEDEC member to get access to the raw card design files. Here are the membership rates for JEDEC, the design files belong to JC45 I think.
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- Thermal has not been a huge issue for us. But we are aware that some enthusiasts level DDR5 modules can run very hot as they are often over-voltaged to 1.4V. Standard UDIMM/RDIMM heatsink plus a gentle breeze should be sufficient even for those ones. In case of running many DDR5 modules in a tightly enclosed space, you will need active cooling even if those are regular 1.1V DIMMs. Their operating temperature is from 0 to +95°C
- Please see the responses I made above
Hi! I knew DDR5 will be a challenge to learn about, but it was even more difficult than I imagined. Many very complex techniques were used to enable DDR5 to operate at that incredible speed. Signal scrambling, DFE, CTLE, and advanced ODT control, just to name a few. The specs are also constantly evolving, some of these functions are also being implemented and new techniques are added to the specs all the time. These new techniques and findings are also crucial and not just nice additions. DDR5 are running so fast for a mostly single ended parallel protocol, any small issue could lead to significant SI issues and every possible optimizations are needed to make it work.
When I first started I thought DDR5 were set when the first spec was published, but now there are even plans to push this technology even faster. Very exciting!
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