Received. Thank you, Lucy!
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| Question | Answer |
|---|---|
| If a routing edge has a tolerance of +/-10 mils, it seems that a 10 mil minimum trace to the edge is a big risk. Too many designers run planes to the edge and expose copper. | Manufacturers typically recommend maintaining a minimum clearance of 10 mils from the board edge to copper. It’s best to allow for a larger margin whenever possible to avoid exposing copper at the edges. |
| For the impedance calculator, is W the value of the trace width, or is W1 considered the trace width? Most calculators that I see treat the copper signal cross section as a rectangle, and this shows it as a trapezoid (which is good) | In our impedance calculator, W represents the trace width. However, due to the etching process, the trace takes on a trapezoidal shape rather than a perfect rectangle. W1 refers to the top trace width, smaller than W. Our calculator accounts for this effect using ΔW (the difference between W and W1), which depends on the initial copper weight. You can refer to the table in the tool for various thicknesses and corresponding ΔW values. Most formula-based calculators assume a rectangular cross-section, which is not accurate. Based on 2D modeling, our tool provides a much more precise calculation. |
| Are there constraint manager setups for these design DDR design rules? | Yes, we offer a product called Constraint Designer EE, which includes wizards to help you create rule sets for DDR and other standard interfaces. Additionally, you can obtain design rules from your memory manufacturer or fabricator (such as Sierra) and import them into Cadence tools. This allows you to implement design-specific rules and streamline the setup process quickly. |
| So should we contact the manufacturer about their panel material to get the stack-up dimensions? | Yes, you should contact your board manufacturer to obtain the complete stack-up information for your board or panel. |
| I am looking for solutions to DDR designs using vias in pads on Class 3 designs and boards, which are .062-.100 thick. The minimum Class 3 via is 24x8, which is problematic on small-pitch DDR BGA chips. Do you have examples or other solutions without compromising Class 3 and higher? | Choosing the right pad size for small-pitch DDR BGA chips in Class 3 designs can be challenging. To ensure compliance without compromising quality, it’s best to consult your fabricator to determine the optimal pad size for your specific board requirements. |
| For DDR4, how concerned do you need to be about cross talk between data lines of the same byte? | You must be very careful about crosstalk in DDR4 data lines within the same byte. To minimize interference, consider routing data lines on alternating layers. I prefer using z-axis separation for certain critical nets to further reduce crosstalk. |
| Do we need back drilling for the DDR4 or DDR5? | The most cost-effective way to manufacture your board is by using blind and buried vias. While back drilling can help reduce signal integrity issues, it increases manufacturing costs and requires more board real estate. |
| Can you confirm that theres no maximum lenght limits as long as they are match in lenght? what is the allowable difference between them? | There is no strict maximum length limit, but the goal is to keep traces as short as possible while ensuring they remain within the required signal integrity parameters. Length matching is important, but you should also use simulation tools to verify signal quality and ensure proper performance. |
| Can you speak to using multiple layers on the CAC lines and compensating for differing via propagation delays (with tight signal to clock)? Rely on simulation tools? How accurate are CAD tools (cadence, altium) in prop delay generally? | We don’t recommend changing layers for CAC lines. In DDR designs, signals should remain on the same layer from the chip to the driver and receiver to maintain signal integrity. You can use our constraint manager to calculate via propagation delays accurately. |