Is it a standard practice to leave high-current traces exposed so they can accumulate solder during the wave soldering process? Will it increase their ability to conduct greater currents?
Hi, Olivia. Leaving traces exposed will expose (sorry, bad pun) you to other problems of excess solder (shorts, spikes) as the assembly leaves the wave. Those issues aside, the result would be inconsistent thickness of trace plus solder. If you need greater current, design traces large enough to conduct that current. Reliability depends on consistency (repeatability) and that begins with design.
Jim Smith
Electronics Manufacturing Sciences, Inc.
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Traces should already be thick enough for the required current.
The extra amount of metal that they could aquire by solder should be minimal (microns), and prone to shorting. It could help, but why bother if you have designed them wide enough already from the start.
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Solder resistance is much higher than copper so there is virtually no benefit to current capacity. Per Dan Beeker’s recent Sierra hosted seminar, his theories on energy traveling through the dielectrics and not in copper also dispell any practical advantage in doing this.
Risk is unintended solder shorting or clearance violations to minimum clearance enclosures. Solder buildup height can become quite large if the exposed copper is also large (I have personal experiences with excessive resulting solder height on exposed copper).
The only situation to selectively allowing solder to build up on the board is if you need solder thieving pads to improve wave soldering of TH pins.
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