How are PCBs with castellated holes handled during panelization?
My understanding is that castellations are created by drilling and plating holes that later get routed through the board edge, leaving a plated half-hole. At what stage does this happen relative to panelization and plating?
If the board edge needs to be routed to form the castellations, how is that managed in a panel that otherwise uses V-scoring or mouse-bites for separation? Are the castellated edges typically routed separately from the rest of the outline?
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Castellations are typically implemented by placing standard plated holes centered on the final board outline, with solder mask pulled back per the fab’s guidelines. After drilling and plating, the board edge is routed through those holes, leaving the plated half-holes.
The castellated edge itself must be routed, but that doesn’t prevent using V-scoring or mouse bites on the other edges of the panel. It’s common for only the castellated side to be fully routed while the rest of the board uses standard panel break methods.
Also keep in mind that even if you don’t provide a panel, the PCB manufacturer will panelize the design internally and add rails or supports as needed. Because castellations involve cutting through plated holes at the edge, it’s important to follow the fabricator’s specific rules for hole size, spacing, and edge clearance.
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The holes are drilled and plated like standard plated through-holes. The difference is simply that they’re placed so the final board outline passes through their center, which creates the castellated half-holes. Drilling and plating happen as usual at the panel level. During depanelization, the castellated edge is routed through those holes, while the remaining edges can still use V-scoring or mouse-bites.
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One practical detail to plan for is panel support near the castellated edge. Because that edge must be routed (you can’t V-score through castellations), fabs usually add rails or breakout tabs along that side to keep the panel rigid during drilling, plating, and routing. Those supports are removed last during depanelization. This is why castellated modules often have one fully routed edge and the rest of the outline handled with V-scores or mouse bites. It’s generally handled at the panel level by the fabricator, but if the castellated edge is mechanically critical, it’s worth flagging it explicitly in the fab notes so they don’t try to score it.
Because the routed cut passes through plated copper, fabs apply tighter routing tolerances on castellated edges to avoid burrs, torn plating, or thin copper lips that don’t solder well. This is why castellated edges are often defined as a separate routed contour with specific tolerances, even though they’re produced in the same drilling and plating steps as the rest of the board. Explicit fab notes help ensure clean edges and consistent plating thickness suitable for reflow.
One additional aspect that’s often overlooked is test and inspection impact. Castellated edges can complicate electrical test and AOI at the panel level. Flying probe or bed-of-nails fixtures usually assume intact pads and vias; half-holes on an edge may be excluded from test coverage or require custom probe rules. For that reason, fabs typically perform electrical test before final routing of the castellated edge, while the holes are still full barrels in the panel. The edge routing that creates the castellations is then treated as a post-test operation during depanelization. This sequencing helps maintain test reliability and avoids false failures on edge features, but it’s another reason castellated edges are handled as a special routed operation rather than just another board edge.