I’m considering designing capacitors directly on a PCB for values in the nF or µF range. The idea is to create the capacitor using two metal layers with a dielectric material in between, effectively building the capacitor into the PCB itself.
Is it feasible to design capacitors this way on a PCB, without purchasing discrete components? How practical is this approach for achieving the desired capacitance values?
Well, first of all you can forget about uF. The good news is what you describe is exactly how it’s done. 3M has a material (C1012) for example that is specified at 10nF per square inch. The dielectric is 0.47 mils thick and it has electrodeposited copper; a dielectric constant of 22 and a dissipation factor of 0.010. It’s performance is similar to X7R dielectrics and has a 3000 volts per mil dielectric strength. So the general idea is you replace a sheet or two of prepreg with this, and on a 4" by 6" board, Bingo, you have 240 nF best case.
@allank has already given a great answer. It is worth putting it into perspective by comparing this with the capacitance you typically get using the thinnest commonly used prepregs which work out at around 50um (which is much thicker than the 3M material that is super thin at just 12um).
With 50um standard prepregs you get around 340pF per square inch, so a 6x4 inch board gives you about 8nF. This is about a 1/30th of the 3M material. That said, it doesn’t mean that the standard buried capacitance is useless, rather this is what normally takes over when the locally placed decoupling capacitors run out of steam at about 50-100 MHz (because the external capacitors become dominated by their internal inductance above this frequency).
Most of the time when you want decent buried capacitance, it is to meet Power Delivery Network (PDN) targets for impedance versus frequency. Having buried capacitance is great but you can ruin the benefit if the inductance between the planes and the components is too high. The classic way to ruin it is to put the buried capacitance close to the middle of the board stack-up. Ideally you want it close to the outer layers. An ideal 6-layer stackup for this would be Sig-GND-PWR-(large gap)-PWR-GND-Sig. The prepregs for separating Sig and GND should be thin (100um or less is good), then this special 3M material is used to separate GND and PWR layers, and so the bulk material between the two PWR layers is what primarily determines the overall thickness.
In the case of 4-layer boards, buried capacitance between (Sig+routed power)-GND-GND-(Sig+routed power) has to be provided through standard prepregs. If you use the 3M material here all the tracks will end up being very low impedance, so standard 50 Ohms tracks or 90 Ohms and 100 Ohms differential pairs become far too thin to manufacture. But if you change one of the GND planes into a power plane, this will have to be at the centre of the board and now the following faults will occur: 1. via inductance from PWR or GND layers to the outer layers ruins the benefit the capacitance would have given you, 2. signals on the outer layers are so far from the planes that making 50 Ohms or 90/100 Ohms differential pairs is almost impossible because they will be very wide tracks. Thus the 3M material does not lend itself to anything less than 6-layer stack-ups.
There are other methods possible to increase the amount of capacitance in the board. Some companies can make boards with thin discrete components inside the laminate. Obviously there are limitations to this. Thin devices like resistors can be included, but capacitors tend to be thicker unless they are 0201 size parts. The benefit of this approach is usually just to make reverse engineering more difficult.
End conclusion, buried capacitance is both useful and necessary. There are special materials that make this easier to achieve, but there are rules the ignoring of which spoils what you would otherwise have gained. Special materials really only give their benefits when boards have at least 6 layers.
Jonathan, thank you for your detailed explanation regarding the feasibility and practicality of designing capacitors directly on a PCB. You mentioned that using specialized materials like the 3M material is beneficial primarily for boards with at least 6 layers, due to the issues with inductance and impedance in thinner boards. Could you provide more insights or best practices for designing 4-layer boards with buried capacitance, especially in terms of mitigating the challenges you highlighted? Additionally, are there any other materials or techniques you would recommend for achieving significant capacitance in such a configuration?
In answer to the request for the best practice for designing a 4-layer PCB with buried capaitance, for typical boards, it comes down to this:
Right stack-up: Sig-GND-GND-Sig. Power is routed on the signal layers. The benefit is that signal transitions between top and bottom layers requires the displacement current path to jump from one GND plane to the other, so putting one or two vias next to the signal via will do the trick perfectly. For high-speed lines like USB3, differential video etc. it is best to have 3 or 4 vias per signal pair.
Route power on the signal layers, then optimise the power traces by using copper pour. This gives you an island of power which is adjacent to the GND plane. To maximise the buried capacitance, you want the minimum distance between the signal and GND layers, so specify that you want this to be a 50-100um (2-4 mils) prepreg. Thinner is better since capacitance is inversely proportional to layer separation.
What not to do. The super high capacitance materials that are available are not intended for use between signal and GND layers (only between PWR and GND layers - which you don’t have on a 4-layer stackup). This is because the Dk factor is so large that it becomes impossible making traces that are 50 Ohms single-ended or 90/100 Ohms differential since they become so thin that they cannot be etched. For all practical purposes, buried capacitance on 4-layer boards must be by using standard FR4 materials.
The principles are not very difficult to apply, and deliver good results if you’ve not spoiled the board with things like GND cuts and passed signals over the cut. When the normal rules are followed, 4-layer boards with USB3 (5Gbps/10Gbps), PCIe (various from 2.5Gbps upwards), Video, Gigabit Ethernet and such like can be implemented without causing trouble in the EMC lab. Even switching power supplies can be implemented on 4-layer boards without causing trouble, but here you really would not want to make the signals or components be placed on top and bottom (just pick one and keep the whole of that regulator circuit on that layer).