Ask your questions PCB manufacturing in this thread and our expert @steve.carney will answer them!
Ask me your questions on all things PCB fab.
Hi Steve, we have a design that requires less than 5% voltage drop from the regulator to a 0.8 mm pitch BGA. Based on our power integrity simulations, I need three 2 Oz layers. This is because of Swiss cheese created by Via antipads. What would be the mimimum width of the copper between adjacent antipads after taking into consideration the manufacturing tolerances? Board is 120 mil thick.
Thanks
I want to make 4 Layer PCB with aluminum heat sink on back (Bottom) layer. All VIAS holes are filled with conductive filler. Can you explain how to proceed this?
For rigid-flex, will bookbinding cost more (how much more) than non-bookbinding? Is there a calculator for PCB layout designers to use to determine the difference in length between flex layers?
Hi, is there an IPC spec requires to fill in back drill holes? Advantages and disadvantages please?
I have a question. I have a 8 layer 3.2mm PCB. During micro section after 3 solder dip we found epoxy cracks. Inner layer interconnection is intact. Do we have to look into the laminate cracks after thermal stress?
How do we use microvias in BGA that will go from top layer to bottom layer. I am using 4 layer PCB Board (1215*16) in Eagle and Fusion 360.
Hi Steve, is there any data to suggest one material is better than the other when it comes to board level reliability (BLR) testing?
Hi Steve!! How do we avoid offset issues in mechanical drilling?
Hi Steve, my question is about how to substantiate flammability for FR-4 Printed Circuit Board material. I used to just say that it was UL 94-V0 rated. But I have heard rumors that the 94-V0 rating is no longer sufficient. Is that true, and if so how do I substantiate the flammability of FR-4 short of burning it?
Well, in truth I don’t believe anyone can. We could perhaps generate a matrix of possibilities…
You see, Ohm’s laws (and Kirchoffs too for that matter) have three variables. Voltage, Resistance, and Current. One of them can be unknown but not two. Now add to that the effect of location – is the power pin on the periphery? In the center with adequate space? Or right in the middle of one of the quads? How many layers is he flowing thru, what distance total, and so on.
If you could make a rough sketch and provide some sample values we could guess much more effectively. My only comment is that having an 0.8 mm pitch is very favorable.
Typically, if we’re building a 4-layer board, it is better to put the aluminum heat sink in the middle, you’d have less warpage issues. If not, you can still put it on the back. We will drill a clearance hole in the aluminum plate that’s larger than the via diameter, then we fill the clearance hole with epoxy and laminate it to the inside or outside of the board, whichever you want. Then we drill the final via holes.
It’s better to fill the back drill holes because they collect debris and cause shorts and contamination issues.
You have a delamination problem which will become worse over time. One of the main reasons for doing thermal stress is to check for delamination and if any is found the board is scraped.
Yes but the amount of data is massive. It really depends on what your design is and what you’re trying to achieve. For instance, there’s data on CAF resistance, stability, electrical properties, thermal stress/expansion, etc. It is best to ask your manufacturer for their advice.
It all depends on your manufacturer’s capabilities to control material movement and registration.
The best thing to do is get the laminate sheet on the material you want to use and that should include all the UL flammability ratings.
Thank you Steve.
Thank you for your response, Steve.