Hi Eric,
On trace impedance design…
Why about EMI? should ground be connected to chassis or not?, the general concept is that it should be connected to one point to improve shielding. However, I heard an expert in avionics say that if they do, the circuit won’t pass the lighting test. How they shield EMI in such a demanding environment then?
What about galvanic isolation? is it OK to isolate signals but not ground?, In a design where both signal AND ground are isolated to the external world, when the external device connects it’s signal ground to chassis (to improve its EMI shielding), it defeats all good intentions to fully protect the circuit from the external environment and its own chassis. And how that modifies your circuit’s EMI emissions?
Hello Eric,
I’m designing a PCB with multiple I2C devices sharing the same power rail as sensitive analog components. How can I minimize power integrity issues caused by I2C bus activity? Specifically, what strategies would you recommend to address potential ground bounce and ensure a reliable power distribution network in a mixed-signal system?
Hi Eric,
When manufacturers recommend adding large amounts of bulk capacitance near their components, there’s often conflicting advice about placement—some suggest close to the regulator, while others recommend close to the load. How can one strike a balance in deciding the optimal placement of bulk capacitance, especially when dealing with recommendations from multiple component vendors in a complex system?
is there any way to calculate optimal placement of these decaps or bulk caps?
Recently I have been measuring near-end and far-end cross talk at very low frequencies (~500kHz) and notice that there is a bump in the cross talk plots at low frequencies. Meaning that there is a peak in cross talk (-60 do -50 dB) at around 500kHz and then it decreases at lower and higher frequencies from that there. These circuits are simply passive interconnects that are either edge launch onto stripline PCBs or ganged coax connectors. It’s difficult for me to understand the mechanism as the wavelength at these frequencies is in the meters. The only idea I have come up with is relating to skin depth and conductivity going down leading to eddy currents on the ground plane. Do you have any insights into low frequency cross talk fr
Hi Eric!!
How can I effectively manage both very high-speed signal traces, like those in 5G technology, and a power supply section with potentially noisy components on the same PCB while aiming to keep the board compact?
Keep the noise on power rails low by using low inductance capacitors near the IC components generating switching noise and use best practices for laying out high speed signals. Just be aware of the problems you are trying to solve.
Sounds like the slightly higher cross talk is a lumped circuit effect. You have an LC resonance on one path coupling to the other path. At the -50 to -60 dB level it could also be in your instruments. This is at the 0.1% coupling range- can easily be a measurement artifact.
Most vendors do not have a clue about the best practice. Always start out by asking what is the problem you are trying to solve. Problem #1 is to reduce the switching noise on the IC’s power rail. This is reduced by adding a low L decoupling capacitor in close proximity to the IC.
Problem #2 is reducing the switching noise from a SMPS. This is solved by adding a large bulk capacitor near the SMPS so that the output resistance and output inductance of the SMPS results in a critically damped RLC circuit.
two different problems, two different solutions.
Use as long a rise time on the I2C bus as practical. This means adjusting the pul-up resistor to not be too small.
Then use low inductance decoupling capacitors on the digital VCC pins of the IC. Add a ferrite filter on the AVCC pins so the noise on the power rail does not pollute the analog power rail of the analog IC.
I’ve recently had some interested students approach me asking how to get started in PCB design… What advice would you give an undergrad ee student about to graduate who would like to explore a career that includes pcb design? Do you have any recommended online/onsite courses or programs you know to be decent?
Not sure of this specific case. We always isolate signals but keep ground (return) connected throughout the system.
galvanic isolation is often about return currents- to manage where they flow. Just make sure the return path is continuous for the signals.
Lightning protection is an exteme case. I am not as familiar with these designs. If your product does not need protection from lightning, don;t design for this extreme case.
For lighting, you can have very large currents, from a high voltage source, with a low impedance source impedance. This means you need a very low impedance path for the lightning current to flow so it does not induce large voltages in your circuit.
Good question. The impedance of a line depends on the line width, the dielectric thicknesses and the Dk values. Usually, the line width is known based on the artwork to +/- the etchback. This can be as much as 1 mil for surface traces that are 1 oz. Find out if the vendor corrected your line width.
in addition to the Dk value, you have to know the dielectric thickness of each layer. Sometimes the only way of knowing is by cross sectioning.
If you know the width and the dielectric thickness, then you can back out the Dk value using hyperlynx or polar to change the Dk value until the predicted Z0 matches what you have measured.
But you are hoping that the vendor uses the same laminate and same thickness for your next board. And hope should never be part of your design strategy. Audit your fab vendor’s process.
Have them read my last book on prototype design: https://us.artechhouse.com/Bogatins-Practical-Guide-to-Prototype-Breadboard-and-PCB-Design-P2268.aspx
Propagation delay is only slightly frequency dependent. This effect is called dispersion. The lossier the material, the larger the dispersion. In FR4, the Dk varies from about 4.6 to 4.4 from 100 MHz to 2 GHz. After that, is is pretty constant with frequency.
Always try to keep the layers on either side of the signals to be ground planes so you have the option to add a return via whenever the signal transitions from layer to layer.
Don’t be too afraid of signal vias. They can be engineered to be nearly transparent up to 28 GHz. Keep in mind, that they are in every high-speed design.
excellent questions. My editorial in the Jan issue of the SI Journal, coming out next month is about exactly this. I think AI design tools will be the wave of the future, but they have to have been trained by an expert, not from the internet.
I don’t know of good tools right now. Stay tuned.
I do not see a need for surface return traces if you have a continuous return plane under the signal. Manging the return current is just as important as managing the signal current.