How do you approach EMI?

Hi everyone.

Sierra has been partnering with a lot of wonderful EMI and EMC experts lately so I figured I’d start a discussion on the topic of EMI.

I’ve been reviewing a few recent designs and it reminded me how much of this is still about tradeoffs. Sometimes we can control emissions at the source with tight return paths and clean stack-ups. Other times, we’re forced into reactive mode, adding ferrites, filters, shields, after the first round of testing surprises us.

So I’m curious to know how do you tackle EMI from the start? Do you follow a checklist, lean on simulation, or just have a few go-to rules that have served you well over time? And how do you balance SI vs. EMI when the two start to fight?

Would love to hear what’s worked (or not worked!) in your experience.

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Can you please exemplify what you meant by SI and EMI starting to fight? I am genuinely curious if you’ve encountered such an issue. We can put PI into the mix as well. There are some aspects of PCB design that routinely present opposing “best practices” to one another, like DFM, DFA and DFT but I haven’t seen the same for EMI, SI and PI yet.

EMI is always a balancing act, and I agree that it’s a mix of proactive design and reactive fixes after testing. Here’s how I typically approach EMI from the start:

  • I start by identifying components or sections of the design that are likely to radiate or be susceptible to EMI. This includes high-speed switching devices, oscillators, and wire harnesses.

  • I also check if any components have a history of EMI issues or require special layout considerations.

  • I try to keep the return paths short, minimizing loop areas, and using solid ground planes.

  • For crystals and oscillators, I pay special attention to their placement and routing, as they can be significant sources of EMI.

  • Wire routing is planned to minimize crosstalk and unintentional antennas.

  • There are times when SI and EMI requirements conflict (e.g., adding series resistors for SI vs. filtering for EMI). In those cases, I prioritize based on the most critical requirement for the application.

  • Despite best efforts, surprises can still happen during EMC testing. That’s why I always plan for some flexibility in the design to add shielding, filters, or other fixes if needed.

What I meant by “SI and EMI starting to fight” is those situations where the layout decisions that optimize signal integrity end up making EMI worse or vice versa. One classic example is high-speed signal routing. For SI, you want controlled impedance, minimal stubs, and clean reference planes which usually means tight, direct routing. But if those signals cross a split plane or return path gets interrupted, suddenly you’ve got a little loop antenna and EMI starts to rear its head.

Another common one is via stitching: great for EMI containment, but if you overdo it or place them too close to sensitive traces, you can start to mess with SI by changing the return path impedance or causing unexpected coupling.

Throw PI into the mix and it gets even more fun. Sometimes the decoupling strategy that helps with power noise (say adding a lot of bulk caps) doesn’t play nicely with the physical space you need to maintain good return paths for signals or creates resonance issues you weren’t expecting.

One approach I’ve found helpful is to integrate EMI considerations into the design process as early as possible, not just at the layout stage. This helps in identifying potential issues before they become critical

Carefully selecting components that are inherently EMI-friendly can make a big difference. For example, choosing low-noise regulators, shielded inductors, and components with integrated EMI filters can reduce the need for additional filtering later on.

A robust stack-up with dedicated ground and power planes is key to minimizing crosstalk and keeping return paths clean. I try to balance EMI and SI needs from the beginning. Guard traces and stitching vias help contain emissions while preserving signal quality.

A solid power distribution network also plays a role, strategically placed decoupling capacitors and well-routed power planes help reduce noise and voltage drop. Despite careful planning, EMI surprises still happen, so I always leave room for late-stage fixes like filters or shields if needed.

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@marko.duksi could you give some examples where DFM, DFA, and DFT fight? I can understand them all (especially Design For Test) fighting against Signal Integrity or even emissions … but when do they fight each other?

Right, that’s a fair question! To be honest, I just went through all the materials on DFA, DFM and DFT I’ve gathered over time and I could not find the one example I was hoping to find, which had me puzzled when I first stumbled upon it. It was something to do with a preference of distributing components with large thermal mass (like high pin count BGAs) in a mirror-like fashion across the two sides of the board. Like I said, I can’t find the original recommendation to detail the consequences of not following it, but intuitively, I’d say it had to do with increased chances of boards warping during assembly. But having such chips on top of each other would double the layer-count and call for blind vias, both of which is not really great for DFM. DFT also goes down the drain. Of course, depending on the power of these chips, this has nightmareish thermal and PI (and therefore SI) implications as well. One thing just follows the other. I was hoping to find this exact example so someone else could possibly elaborate it, but no luck.

Others would be where it is recommended (from DFM perspective) to remove thin solder resist webbing between fine-pitch components’ pads in order to increase bare board yield (due to increased chances of specific fabrication defects when this webbing is too thin). Great, so just where I need the solder-resist dams between the pads the most to increase yields in assembly, I should actually remove them (or the fabricator will) to even fabricate the boards. Personally, I’d rather have boards fail during fabrication (as long as the defects are detectable, of course) than have them fabricated in high yield with no solder-resist between fine-pitch components’ pads, only to discard them after failing tests with assembled components having solder bridges. But maybe it’s just me, I’m just a hobbyist.

And lastly, I totally acknowledge how clashes between DFM, DFA and DFT are far less common than clashes between those three and some of the best practices of SI/PI and controlling EMI. I should not have written they oppose each other routinely. I guess I had such an impression myself, when reality is actually not that bad. That said, no valid examples of a SI vs. EMI fight come to my mind. Taking care of SI necessitates also taking care of PI, which both combined do not hider control of EMI but actually help in doing so. That’s what still puzzles me in the original post.

How to approach EMI is a really big question and as has already been pointed out, one for which there are multiple answers, often working as trade-offs one against another. There has already been a good number of answers given, and quality suggestions along with it. Obviously there is no single answer and because there are many different kinds of products, there will be many cases to consider. A few will require extreme measures to be taken to make emissions or susceptibility low enough for the design as a whole to function as it needs to.

When we implement our designs on a PCB suggestions from manufacturers often result in adding common mode chokes, ferrites, shielding cans and many other things and this adds to the cost. Naturally we want to keep the cost down but this is hard to do if we choose to follow all the manufacturer’s advice. But often the advice is given as a precaution, though we sometimes interpret it as a mandatory.

It is tempting to say that the PCB itself is often one of if not the most important component that determines the EMI the product will unintentionally emit or capture. In many designs, it is fair to say that unless there are very special needs, most EMI issues can be solved by appropriate PCB design. Of course, you might say that your product can’t stand the cost of a 4-layer PCB, but it may be that this solution is cheaper than a 2-layer PCB with additional ferrites, filters and whatever else. Making a 2-layer PCB work from an EMI perspective can be tricky at best, but a correctly implemented 4-layer board without these extra parts can work out quite a lot easier to design and be the more cost effective solution.

Excepting trivial circuits, 1-layer PCBs are very difficult for controling EMI, but if the solution is to put it in a can, would it have been easier to skip the can and use a 2-layer, or better a simple 4-layer stack-up? This may also facilitate a smaller PCB too which also saves cost.

This is a rather long preamble to answering the first question, but it sets the scene. When I think about the EMI concerns on a new design, my first thought is “does it make sense to design this as a 4-layer (S-G-G-S) board?” If it does, then I’m happy because most of the varied things that I get asked to design can be implemented in this way with a very low EMI risk. If the answer is “no” but it is because 4 layers is not enough, then adding more is not a big deal, and again I expect an easy “pass” at the EMI test lab. I get a lot more concerned if it has to come down to a 2-layer board, as whatever parts have to be added to make this pass, it is much more of a struggle. Single layer designs I won’t do unless they are really simple things like just power relays and very low-speed things only, and it can be made very small.

It is perhaps useful to add a bit of context. About half of the boards I design are multiprotocol routers of one sort or another. They have 10Gbps USB, 1Gbps Ethernet, HDMI, various kinds of serial interfaces, Cellular, WiFi/Bluetooth, LORA, and multiple switching PSUs. For this a 4-layer PCB is a consistent easy win at the EMI labs. It doesn’t require extra protection on any of the interfaces to the outside world. It is about as good whether the unit is in a metal case, a plastic case or no case at all. With a 4-layer board, the only time I have to think further about EMC is if something special is needed, like ability to withstand a higher voltage while surge testing etc.

It is quite justifiable to say that the best investment to make EMI a much lower risk is quality training. The most recent example that I recall from Sierra Circuits was the Rick Hartley training course back in February. Learn how to design PCBs right and a great deal of the EMI issues vanish. The best courses don’t just tell you what to do, they explain why. Once you know the principles, the application of the rules makes a lot more sense, and may give you a good steer when things can’t be done perfectly. Look out for the training courses Sierra Circuits host and invest in your future.

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Ahh … though if it is the components rather than just their land patterns, I’m not sure assembly really benefits enough from “flatter” to make up for having two complicated sides, or for heavy components having to go through upside down on the second pass.

But removing soldermask slivers is indeed a good example, and I suppose so are the rules about silk screen clearance.

no valid examples of a SI vs. EMI fight come to my mind.

Some SI workarounds are the equivalent of yelling; you do get a stronger signal, but the neighbors are likely to hear it too.

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