We are designing a board to make a static electric field with constant voltages in the vertical direction, and exponentially varying voltages in the horizontal direction. Voltages vary from -5000V on the left side down to -5 V near the middle, and then 5V to +5000v. There is no Current–(the traces do not lead to any component). To do this we have straight traces running vertically. Since the voltage vary exponentially, the voltage difference between the traces is greatest at the highest voltages.
Questions:
-
Using the trace spacing calculators, Internal layers can withstand the highest voltage differences, so our plan is to but a dialectric layer over the traces. (i.e. no copper on the outer layer). Is there a lower limit on the thickness of the dialetric layer before the internal layer is not considered internal? How thin can be manufactured?
-
To supply the voltages we are using a resistor divider network on a board that will plug in to what we described above (opposite side from the verticale traces). We have preliminarily chosen two 2x40 surface mount male pin connectors. 100 mil spacing, (skipping some pins at the highest voltage differences). For surface copper, the on line tool indicates a conformal coating is best. The coating would need to cover all the copper pads and under the connector (~75mil standoff height). The male pins would need to be masked. I have no experience with conformal coatings. What type should we use? Does Sierra Circuits provide this service? Anything else we need to be aware of?
Thanks,
Greg