What are the current best practices for connecting digital ground, analog ground, and chassis ground in mixed-signal PCBs?
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General recommendation is not splitting analog and digital grounds. There are isolated cases in which keeping them separate has some advantages but generally those situations have very defined and isolated circuits which should be kept physically separate from each other. If they need a common tie point, that usually is back at the power supply source. What you want to avoid is having routing cross splits in grounds and many times, datasheet recommendations can be incorrect in this matter.
Chassis ground is another matter as that might be tied directly or through filters depending on the situation and testing results.
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Keep return domains low-impedance and contiguous where possible: use a single solid reference plane for fast digital signals, route analog sensitive circuitry so its return flows on the same plane, and bond chassis ground to PCB ground at one controlled point (single-point or low-impedance tie) with careful EMI filtering/transition (RC, common-mode choke, or Y-caps) as required by safety/ESD. Avoid splitting planes for routine separation, prefer partitioning by component placement and routing with controlled return paths. If isolation is required (e.g., high voltage), use galvanic isolation and treat the isolated ground as a separate domain with defined tie points.
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For mixed-signal ICs like ADCs and DACs, treat them as analog parts: tie AGND/DGND pins into the analog section of the plane and decouple them locally with small ceramics placed right at the pins. This keeps digital switching currents confined to tiny loops instead of polluting the wider ground. If the device drives heavier digital activity, you can add ferrite beads on the digital supply lines to further isolate noise from sensitive analog returns.
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Another important piece is how you validate your grounding approach. Even with a unified plane, mixed-signal designs can surprise you because of placement and return-current density. A good practice is to think in terms of current loops instead of just plane areas: keep digital loops short and away from sensitive analog return paths. Place high-speed digital ICs so that their return currents don’t cut across analog regions, and cluster sensitive analog blocks close to their ADC/DAC inputs to minimize shared return impedance.
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How do you decide between a direct chassis-to-PCB ground tie vs. using capacitive/filtered connections?
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It depends on the product’s EMI and safety requirements. For low-frequency immunity (like ESD), a direct low-impedance bond to chassis usually works best. For high-frequency noise, capacitors or RC networks let you shunt unwanted signals to chassis without creating large DC return paths. In practice, many designs combine both, a direct connection to chassis for safety/ESD and capacitive ties for high-frequency EMI suppression. Testing in the actual enclosure often dictates the final choice.
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