I’m currently in the process of designing a 4-layer PCB with the following layer stackup:
SIG-PWR-GND-SIG(includes an RF antenna track)
I’ve connected all the 5V and 3.8V connections from the top/bottom layers to the power plane using through-hole vias. Given that the power plane and ground plane are adjacent to each other with a dielectric thickness of 1mm, I’m concerned about the potential capacitance between the power and ground planes and whether it could lead to any issues.
Should I consider removing extra copper from the power plane to mitigate any potential problems? Additionally, since I’ve utilized through-hole vias instead of blind vias, there are unused vias (via stubs) in the PCB. Could these floating vias cause any issues with the functionality of the PCB?
Normally the capacitor formed by the power plane and ground plane act to bypass noise from power to ground which is beneficial. The presence of via pads terminating on the outside layers shouldn’t be an issue unless they are in the way.
Indeed, having power and ground planes adjacent to each other does add capacitance between them. This is because when two conductors are separated by an insulator, they essentially form a capacitor. However, this arrangement of distributed capacitance between power planes is actually beneficial rather than problematic. It’s considered a desirable property in PCB design as it helps stabilize and filter power distribution, contributing to better signal integrity and reduced noise levels.
It varies based on the signals transmitted through the vias and whether the via stubs could pose any issues. For RF and high-speed data signals, there’s a possibility of impact, but for low-frequency signals, it’s less likely to cause problems.