Microvia reliability questions come up regularly during HDI layout and DFM reviews, so I wanted to start a thread on how designers approach microvia design to avoid failures during fabrication and assembly.
These tiny vias are laser-drilled holes with a diameter of 6 mil or less, used in HDI boards to connect adjacent layers.
Unlike through-hole vias, they only span one or two dielectric layers, which makes them ideal for fine-pitch BGA escape routing and dense interconnects. However, their small geometry makes them more susceptible to thermal stress failures, particularly during reflow.
Most microvia failures are not random, they’re driven by:
- CTE mismatch between copper and dielectric
- Stress from repeated lamination cycles
- Weak plating or poor via structure
The goal of reliable microvia design is to control geometry, material choice, stack-up, and process constraints so the via survives thermal cycling without cracking or separating at the interfaces.
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From a layout standpoint, the most important parameters to control are aspect ratio, capture pad geometry, and via configuration.
Maintaining a maximum aspect ratio of 0.8:1 ensures uniform plating and prevents thin copper at the via bottom. Limiting the microvia diameter to 6 mil avoids drilling instability and taper variation. The capture-pad to target-pad distance should be kept to 10 mil or less for predictable laser depth control.
For via configuration, staggered microvias are generally preferred over stacked ones. Staggered microvias reduce vertical stress accumulation and survive more thermal cycles than stacked vias. When staggering, maintain a vertical offset greater than the via diameter between adjacent microvias, and apply a minimum 2 mil spacing between staggered structures for drill stability and plating flow.
Stacked microvias are appropriate when routing density is extremely high, such as for fine-pitch BGAs, and layer-to-layer registration is critical. They allow smaller diameters of 4-5 mil, but increase cost.
Also, keep the solder mask expansion at 0 mil around microvias. Specifying zero solder-mask expansion around microvias prevents solder flow into via edges. Partial or slotted mask openings should be avoided, as they trap flux and create conductive residues.
Material selection and stack-up configuration are just as critical as geometry. Choose dielectric materials that are compatible with laser drilling and sequential lamination cycles. High-quality resin systems with flat or spread glass structures are suitable for laser drilling, as the glass structure directly affects drilling quality, plating adhesion, and thermal expansion behavior during reflow cycles. Materials such as Isola FR408HR, FR370HR, I-Speed, and Nelco N7000-2HT are well-suited for this application.
For stack-up, design in accordance with IPC-2226 standards. IPC-2226 defines standard HDI build-up types to ensure the manufacturability of microvias and cost-efficient production. These structures ensure efficient heat dissipation and prevent thermal stress on the microvias.
For testing, include D-coupons in your panel. D coupons, designed in accordance with IPC-2221 Appendix A or B, are the primary test structures used to verify microvia reliability under thermal and electrical stress. A D coupon is considered failed if the resistance of the via chain increases by more than 5% during thermal cycling.
In your fab notes, specify the fill type (non-conductive or conductive), the number and location of test coupons, hole sizes, plating requirements, and whether the via needs a planar capped surface.
For a detailed breakdown of all six design tips, including material selection, IPC standards, and test methods, read: How to Design Reliable Microvias in Your PCBs.
