# \#pcb-design **URL:** https://sierraconnect.protoexpress.com/tag/pcb-design/125.md [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) --- ## [Design Considerations for LPDDR4/LPDDR5 Signal Probing](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321)
**Author:** [@harshitshakya49](https://sierraconnect.protoexpress.com/u/harshitshakya49)\ **Replies:** 2\ **Last updated:** [July 30, 2026, 1:36pm UTC](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321 "2026-07-30T13:36:09Z")
Hi everyone, We are designing two different boards: - Board 1: LPDDR4 - Board 2: LPDDR5 For both boards, we need to perform signal probing during hardware validation and debugging. I would like to know the recommend… --- ## [PCB Live Chat with Greg Albers & Steve Carney](https://sierraconnect.protoexpress.com/t/pcb-live-chat-with-greg-albers-steve-carney/4014)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 10\ **Last updated:** [July 24, 2026, 10:20pm UTC](https://sierraconnect.protoexpress.com/t/pcb-live-chat-with-greg-albers-steve-carney/4014 "2026-07-24T22:20:49Z")
Thanks for your interest in our very first PCB live chat! Click the link below to register! Already registered? I’ll send you the Zoom link by email in a few minutes. In the meantime, you can start posting your questio… --- ## [SELV vs FELV Isolation Requirements](https://sierraconnect.protoexpress.com/t/selv-vs-felv-isolation-requirements/4276)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 3\ **Last updated:** [July 24, 2026, 2:19pm UTC](https://sierraconnect.protoexpress.com/t/selv-vs-felv-isolation-requirements/4276 "2026-07-24T14:19:41Z")
In a 230 V AC system with an RS-485 Modbus interface, what happens if the PCB cannot maintain the creepage and clearance distances required for SELV isolation? Specifically: Does that mean the entire RS-485 network mus… --- ## [Include Serial Number on Board](https://sierraconnect.protoexpress.com/t/include-serial-number-on-board/4045)
**Author:** [@allen.morrison](https://sierraconnect.protoexpress.com/u/allen.morrison)\ **Replies:** 6\ **Last updated:** [May 12, 2026, 7:45pm UTC](https://sierraconnect.protoexpress.com/t/include-serial-number-on-board/4045 "2026-05-12T19:45:32Z")
Howdy, How would I go about adding a unique serial number to each board in an order that Sierra Circuits fabricates? For example, on the silkscreen, I have the part number and revision and a place for the serial number… --- ## [Webinar: AI Enabling New Mindset for Electronics R&D](https://sierraconnect.protoexpress.com/t/webinar-ai-enabling-new-mindset-for-electronics-r-d/2804)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [April 24, 2026, 4:26pm UTC](https://sierraconnect.protoexpress.com/t/webinar-ai-enabling-new-mindset-for-electronics-r-d/2804 "2026-04-24T16:26:53Z")
Thank you for your interest in our webinar on improving AI enabling new mindset for electronics R&D. It was presented by Sergiy Nesterenko, Founder and CEO of Quilter. Missed the webinar? Click the below link to watch t… --- ## [CAN Bus PCB Routing – Two Nodes with Unequal Distance to Single Connector](https://sierraconnect.protoexpress.com/t/can-bus-pcb-routing-two-nodes-with-unequal-distance-to-single-connector/3985)
**Author:** [@shyammarimuthu123](https://sierraconnect.protoexpress.com/u/shyammarimuthu123)\ **Replies:** 9\ **Last updated:** [April 18, 2026, 4:14am UTC](https://sierraconnect.protoexpress.com/t/can-bus-pcb-routing-two-nodes-with-unequal-distance-to-single-connector/3985 "2026-04-18T04:14:44Z")
Hi Friends, I am working on a PCB design with the following CAN architecture: Two MCUs on the same board Each MCU has its own CAN transceiver Both transceivers are connected to a common CANH and CANL connector … --- ## [PCB GLOSSARY: Signal Skew](https://sierraconnect.protoexpress.com/t/pcb-glossary-signal-skew/3734)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [December 5, 2025, 10:44am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-signal-skew/3734 "2025-12-05T10:44:16Z")
Signal skew is the timing mismatch or variation in propagation delay between multiple electrical signals that are intended to switch or arrive simultaneously at a destination. This timing misalignment is a critical c… --- ## [PCB Via Types and Their Applications](https://sierraconnect.protoexpress.com/t/pcb-via-types-and-their-applications/3535)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [September 9, 2025, 3:13pm UTC](https://sierraconnect.protoexpress.com/t/pcb-via-types-and-their-applications/3535 "2025-09-09T15:13:00Z")
PCB vias are plated holes that establish an electrical connection among different layers of a PCB. Vias enable the miniaturization and complexity that advanced electronic designs demand, allowing signals and power to … --- ## [PCB Glossary: Return Path](https://sierraconnect.protoexpress.com/t/pcb-glossary-return-path/3531)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 1\ **Last updated:** [September 6, 2025, 2:08am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-return-path/3531 "2025-09-06T02:08:40Z")
A return path in a PCB refers to the low-impedance path through which current flows back to the source after passing through a circuit component. The return current typically traverses through ground planes or adjacent … --- ## [PCB Glossary: Decoupling Capacitors](https://sierraconnect.protoexpress.com/t/pcb-glossary-decoupling-capacitors/3413)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [August 1, 2025, 1:23pm UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-decoupling-capacitors/3413 "2025-08-01T13:23:06Z")
A decoupling capacitor (decap) is a passive electronic component placed between a power supply and an IC on a PCB. Its primary function is to filter out voltage spikes and high-frequency noise, providing a stable DC supp… --- ## [PCB Glossary: Fiducials](https://sierraconnect.protoexpress.com/t/pcb-glossary-fiducials/3365)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 15, 2025, 1:33pm UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-fiducials/3365 "2025-07-15T13:33:23Z")
Fiducials are reference marks on a PCB used to align and calibrate automated assembly equipment. These markers serve as visual targets for aligning the board during pick-and-place, solder paste printing, and automated op… --- ## [Trace width guidelines for single-sided PCBs](https://sierraconnect.protoexpress.com/t/trace-width-guidelines-for-single-sided-pcbs/3264)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 7\ **Last updated:** [June 18, 2025, 3:46pm UTC](https://sierraconnect.protoexpress.com/t/trace-width-guidelines-for-single-sided-pcbs/3264 "2025-06-18T15:46:18Z")
I use relatively thick traces on all my boards, even for signals that could probably use 5–8 mils. I usually go with 12 mil traces and 12 mil clearance as my minimum, and for power lines (except ground) I often use 40–50… --- ## [Webinar: Resolving High-Speed PCB Design Challenges](https://sierraconnect.protoexpress.com/t/webinar-resolving-high-speed-pcb-design-challenges/3119)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [May 21, 2025, 4:17pm UTC](https://sierraconnect.protoexpress.com/t/webinar-resolving-high-speed-pcb-design-challenges/3119 "2025-05-21T16:17:40Z")
Thank you for your interest in our webinar on resolving high-speed PCB design challenges. It will be presented by the Sierra Circuits team of design engineers. Already filled out the form on our registration page? You a… --- ## [OPEN DISCUSSION: Which PCB design software do you use and why?](https://sierraconnect.protoexpress.com/t/open-discussion-which-pcb-design-software-do-you-use-and-why/3156)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 5\ **Last updated:** [May 12, 2025, 3:21pm UTC](https://sierraconnect.protoexpress.com/t/open-discussion-which-pcb-design-software-do-you-use-and-why/3156 "2025-05-12T15:21:56Z")
Tell us your go-to PCB design software—what makes it your favorite, and what feature can you not live without? --- ## [Optimal Solder Mask Expansion: 1:1 or Fabricator-Defined?](https://sierraconnect.protoexpress.com/t/optimal-solder-mask-expansion-1-1-or-fabricator-defined/2993)
**Author:** [@Sophia](https://sierraconnect.protoexpress.com/u/Sophia)\ **Replies:** 9\ **Last updated:** [March 25, 2025, 4:09pm UTC](https://sierraconnect.protoexpress.com/t/optimal-solder-mask-expansion-1-1-or-fabricator-defined/2993 "2025-03-25T16:09:10Z")
I’ve been using a 1:1 ratio between my pads and solder mask openings in my Gerber files, as I understand that most fabricators prefer this approach. From what I’ve heard, many manufacturers apply their own global solder … --- ## [PCB GLOSSARY: Parasitic capacitance](https://sierraconnect.protoexpress.com/t/pcb-glossary-parasitic-capacitance/2992)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [March 17, 2025, 11:36pm UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-parasitic-capacitance/2992 "2025-03-17T23:36:05Z")
Parasitic capacitance (stray capacitance) is unintended capacitance that arises between conductive elements on a PCB due to their proximity and electric field coupling. This can degrade signal integrity, cause crosstalk,… --- ## [High power board-to-board interconnect between two PCBs](https://sierraconnect.protoexpress.com/t/high-power-board-to-board-interconnect-between-two-pcbs/2963)
**Author:** [@shysd](https://sierraconnect.protoexpress.com/u/shysd)\ **Replies:** 2\ **Last updated:** [March 6, 2025, 11:54pm UTC](https://sierraconnect.protoexpress.com/t/high-power-board-to-board-interconnect-between-two-pcbs/2963 "2025-03-06T23:54:34Z")
Hello everyone, I am working on a DC link capacitor bank design which is to be mounted inside an enclosure. The capbank assembly consists of two PCBs with capacitors soldered on them (8 x 1000 uF, arranged in a 4 x 2 gr… --- ## [OPEN DISCUSSION: What are your thoughts on the future of AI in PCB design?](https://sierraconnect.protoexpress.com/t/open-discussion-what-are-your-thoughts-on-the-future-of-ai-in-pcb-design/2803)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 8\ **Last updated:** [February 5, 2025, 4:08pm UTC](https://sierraconnect.protoexpress.com/t/open-discussion-what-are-your-thoughts-on-the-future-of-ai-in-pcb-design/2803 "2025-02-05T16:08:53Z")
AI has made its way into various aspects of engineering, including PCB design. From automating design layouts to optimizing performance for high-speed circuits, the possibilities seem endless. But where is this heading, … --- ## [INFOGRAPHIC: PCB Design Workflow](https://sierraconnect.protoexpress.com/t/infographic-pcb-design-workflow/2780)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [January 7, 2025, 2:34pm UTC](https://sierraconnect.protoexpress.com/t/infographic-pcb-design-workflow/2780 "2025-01-07T14:34:21Z")
A successful PCB design requires attention to layout guidelines and close collaboration between designers and manufacturers. Below are the key steps in printed board design workflow to ensure your project transitions … --- ## [5 Typical PCB Design Challenges With Solutions for Engineers](https://sierraconnect.protoexpress.com/t/5-typical-pcb-design-challenges-with-solutions-for-engineers/2782)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 0\ **Last updated:** [January 7, 2025, 4:57pm UTC](https://sierraconnect.protoexpress.com/t/5-typical-pcb-design-challenges-with-solutions-for-engineers/2782 "2025-01-07T16:57:58Z")
Originally published at: https://www.protoexpress.com/blog/pcb-design-challenges-with-solutions-for-engineers/ With the rapid advancements in AI and IoT technologies, modern circuit designs demand careful attention t… --- ## [How Modular PCB Design Method Simplifies Complex Layouts](https://sierraconnect.protoexpress.com/t/how-modular-pcb-design-method-simplifies-complex-layouts/1837)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [September 19, 2024, 7:11am UTC](https://sierraconnect.protoexpress.com/t/how-modular-pcb-design-method-simplifies-complex-layouts/1837 "2024-09-19T07:11:39Z")
Originally published at: https://www.protoexpress.com/blog/how-modular-pcb-design-method-simplifies-complex-layouts/ In a modular PCB design method, a complex circuit board is divided into smaller modules. Each perfo… --- ## [Best PCB DFM Practices to Avoid Manufacturing Defects](https://sierraconnect.protoexpress.com/t/best-pcb-dfm-practices-to-avoid-manufacturing-defects/1103)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [July 18, 2024, 11:32pm UTC](https://sierraconnect.protoexpress.com/t/best-pcb-dfm-practices-to-avoid-manufacturing-defects/1103 "2024-07-18T23:32:32Z")
If you’ve filled out the form on our registration page, you are registered and will receive an email confirmation within 5 minutes. Or fill out the form on the link below to register. --- ## [Ask Me Anything about PCB Design Constraints](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-pcb-design-constraints/1511)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 4\ **Last updated:** [June 25, 2024, 7:52pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-pcb-design-constraints/1511 "2024-06-25T19:52:03Z")
Participate in our next Ask Me Anything about design constraints where you can ask us questions on: Best practices for managing design constraints Tips for optimizing layout and routing Strategies for mitigating common… --- ## [Case Study: Resolving EMI and PCB Routing Issues in a Medical Optical Scanner](https://sierraconnect.protoexpress.com/t/case-study-resolving-emi-and-pcb-routing-issues-in-a-medical-optical-scanner/1269)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 4\ **Last updated:** [April 18, 2024, 5:47pm UTC](https://sierraconnect.protoexpress.com/t/case-study-resolving-emi-and-pcb-routing-issues-in-a-medical-optical-scanner/1269 "2024-04-18T17:47:09Z")
Originally published at: https://www.protoexpress.com/blog/case-study-resolving-emi-and-routing-issues-in-medical-optical-scanner/ In a recent collaboration, our PCB design engineers worked on a medical circuit board… --- ## [Ask Me Anything with Amit Bahl (DFM)](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-amit-bahl-dfm/1027)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 17\ **Last updated:** [February 22, 2024, 10:19pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-amit-bahl-dfm/1027 "2024-02-22T22:19:47Z")
@ThePCBGuy will answer your questions on DFM. Start posting now!