# Webinar: Via Design Techniques to Build Reliable PCBs
**URL:** https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222
**Category:** Webinars & Events
**Tags:** via, webinar
**Created:** [October 9, 2023, 10:15pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222 "2023-10-09T22:15:19Z")
**Posts on this page:** 20
**Page:** 1
### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 9, 2023, 10:15pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/1 "2023-10-09T22:15:19Z")
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### Author:  [@steve.carney](https://sierraconnect.protoexpress.com/u/steve.carney)
#### Post date: [October 10, 2023, 7:06pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/2 "2023-10-10T19:06:59Z")
I’ll be answering questions in this webinar. Join us!
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 9:59pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/3 "2023-10-25T21:59:06Z")
I will post all the questions asked during the webinar below. Feel free to add more to this thread and tag our [@Sierra\_Experts](https://sierraconnect.protoexpress.com/groups/sierra_experts).
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 9:59pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/4 "2023-10-25T21:59:15Z")
I would like to know the fabrication method difference of PCB and IC substrate. Thanks
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:01pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/5 "2023-10-25T22:01:42Z")
How many GND via should surround a single signal via in a coaxial via structure for impedance matching?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:01pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/6 "2023-10-25T22:01:54Z")
Is there a possibility in the future to reach smaller annular ring for laser vias and mechanical vias like having annular ring around 2 mils and what is min drill diameter that we might be able to reach with both types , since smaller via structures are needed for 224G applications ?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:02pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/7 "2023-10-25T22:02:10Z")
What is the difference of positive and negative etchback?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:02pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/8 "2023-10-25T22:02:27Z")
What is the meaning of ‘controlled depth’ for blind and buried via?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:02pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/9 "2023-10-25T22:02:49Z")
What advantage does positive etchback give in terms of reliability?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:03pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/10 "2023-10-25T22:03:19Z")
What about annular ring of buried vias?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:03pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/11 "2023-10-25T22:03:53Z")
Is there an advantage (cost, etc.) for filling just some vias as opposed to filling all vias?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:04pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/12 "2023-10-25T22:04:13Z")
Which is recommended way to reduce the stubs in high-speed designs?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:04pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/13 "2023-10-25T22:04:56Z")
What’s the best via to plane clearance? What’s the minimum designers can get away with while maintaining good DFM?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:05pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/14 "2023-10-25T22:05:16Z")
How many GND via should surround a single signal via in a coaxial via structure for impedance matching?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:05pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/15 "2023-10-25T22:05:30Z")
Is there any risk of having \>10:1 aspect on thru drilled vias?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:05pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/16 "2023-10-25T22:05:44Z")
Recommended spacing for stitching vias?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:06pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/17 "2023-10-25T22:06:20Z")
Putting more via means adding cost, so what would be the optimal number of GND vias to surround one signal via?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:06pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/18 "2023-10-25T22:06:36Z")
How we can judge signal integrity after via design?
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### Author:  [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [October 25, 2023, 10:07pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/19 "2023-10-25T22:07:26Z")
How to calculate the aspect ratio of blind and buried vias?
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### Author:  [@steve.carney](https://sierraconnect.protoexpress.com/u/steve.carney)
#### Post date: [October 25, 2023, 10:13pm UTC](https://sierraconnect.protoexpress.com/t/webinar-via-design-techniques-to-build-reliable-pcbs/222/20 "2023-10-25T22:13:55Z")
For IC substrate, if the trace and space and vias are smaller, then it would go through more or less the same processes, however, we would use different parameters for the process. Do you have a specific question around a specific process? Some of the variations in process have been named, semi-additive process, for example, where you start with a very thin copper foil. Hope that helps.
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