# WEBINAR HIGHLIGHT: Manufacturing Stacked Vias

**URL:** <https://sierraconnect.protoexpress.com/t/webinar-highlight-manufacturing-stacked-vias/3110>\
**Category:** High Speed and Frequency\
**Tags:** hdi, via\
**Created:** [April 21, 2025, 4:34pm UTC](https://sierraconnect.protoexpress.com/t/webinar-highlight-manufacturing-stacked-vias/3110 "2025-04-21T16:34:31Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [April 21, 2025, 4:34pm UTC](https://sierraconnect.protoexpress.com/t/webinar-highlight-manufacturing-stacked-vias/3110/1 "2025-04-21T16:34:31Z")

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[https://protoexpress.wistia.com/medias/x5vo5u1tfc](https://youtu.be/jNh7nJfoDOw?si=YCxA73hPSCZG1YNA)

This part of our webinar on [via design and manufacturing](https://youtu.be/jNh7nJfoDOw?si=YCxA73hPSCZG1YNA) highlighted important considerations when choosing between stacked and staggered vias for high-density interconnect designs.

**Key points:**

- **Stacked vias:**

- **Staggered vias:**

**Example shared:**

- An 8-layer board with:
  - Vias from layer 1 to 3, 1 to 4, and 5 to 8.

- Emphasis on maintaining an **aspect ratio of 0.75** , such as using a 6 mil drill for 5 mil dielectric layers.
- Design must balance:
  - **Drill size constraints**
  - **Material stack-up and press-out thickness**
  - **Controlled impedance requirements**
  - **Available space**

Clear communication with the fabricator is essential to ensure materials, stack-up, and via structures meet all performance and manufacturability targets. The interplay between these factors is critical in tight, high-performance layouts.

Watch the full webinar [here](https://youtu.be/jNh7nJfoDOw?si=YCxA73hPSCZG1YNA).