# TRUE OR FALSE: EMC Edition

**URL:** <https://sierraconnect.protoexpress.com/t/true-or-false-emc-edition/3094>\
**Category:** EMC and EMI\
**Tags:** emc\
**Created:** [April 17, 2025, 4:20pm UTC](https://sierraconnect.protoexpress.com/t/true-or-false-emc-edition/3094 "2025-04-17T16:20:45Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [April 17, 2025, 4:20pm UTC](https://sierraconnect.protoexpress.com/t/true-or-false-emc-edition/3094/1 "2025-04-17T16:20:45Z")

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[![true or false trace talks ignacio emc](https://global.discourse-cdn.com/sierraconnect/original/1X/ace502a9d4b7647489a14142441b71378302b742.jpeg)](https://youtu.be/oTvyAXBILuU?si=aGS0iQoo4Fb8ZIy4&t=3673)

**Q: Components with high current draw are less likely to generate EMC issues. True or false?**

**A: False.**

> That should be obvious—high current can often correlate with more EMC issues.

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**Q: Can reducing trace lengths help minimize EMI issues?**

**A: Yes, it can help.**

> It’s not a silver bullet, but shorter traces generally improve EMI performance.

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**Q: Does reducing PCB size help with EMC performance?**

**A: Yes.**

> Smaller PCBs mean shorter traces and better containment of energy, assuming the operating frequency remains the same.

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**Q: If you switch from 5 mil to 2 mil trace/space technology and keep PCB cost constant, does the smaller board size improve EMC?**

**A: Yes, if frequency remains the same.**

> Tighter layout = better energy control and reduced EMI.

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**Q: Does using a thicker PCB have any impact on EMC performance?**

**A: Yes, and this is often underestimated.**

> Thicker boards increase the distance between signal traces and reference planes, which can worsen EMC performance.

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**Q: Is there a general rule for trace spacing to minimize crosstalk?**

**A: Yes.**

> Keep traces spaced at least 3x the trace width apart.  
> But in high-density PCBs, this isn’t always practical.

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**Q: So what’s the workaround when space is limited?**

**A: Move traces closer to the ground plane.**

> By reducing the dielectric thickness (bringing traces closer to the plane), you confine the energy and reduce EMI and crosstalk.

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**Q: So thinner PCBs are better for EMC?**

**A: Often, yes.**

> Less separation between signal and ground means better performance. But you must also consider stack-up design.

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**Q: What’s important in stack-up design for EMC?**

**A: Coupling signal layers to reference planes.**

> For example, on a 4-layer board, the signal layers should be close enough to the ground plane to serve as effective references. Don’t assume a distant layer can function as a reference.

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### ✅ **Rule of thumb (validated):**

**The more separation you have between a signal layer and its reference plane, the worse your EMC performance will be.**

> Signal-ground proximity is crucial. Design your stack-up accordingly.

**Watch [Trace Talks EP 8](https://youtu.be/oTvyAXBILuU?si=4jngroaonXVXIH9l) with Ignacio de Mendizábal.**