# \[SPOT THE FLAW\] CLUE: It's overlapping

**URL:** <https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786>\
**Category:** General\
**Created:** [January 8, 2026, 2:40am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786 "2026-01-08T02:40:30Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [January 8, 2026, 2:40am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/1 "2026-01-08T02:40:30Z")

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![flaw](https://global.discourse-cdn.com/sierraconnect/original/1X/c058756fbc65220f133e4faeeaf6a21924bed965.jpeg)

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**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\
**Post date:** [January 8, 2026, 7:34pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/2 "2026-01-08T19:34:29Z")

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CGND copper and GND copper are overlapping.

Design rules should flag this clearance violation under normal circumstances.

There are times when users want to do this on purpose. It is best to use a Net-Tie type footprint in order to properly manage this situation. You should also be sure your supplied netlist has specified net-tied connections or you may find the fabricator has placed the order on hold until it has been verified as an intended design element.

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**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [January 9, 2026, 7:24pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/3 "2026-01-09T19:24:06Z")

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Yup… 🙂

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<div class="post-metadata">

**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [January 9, 2026, 10:06pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/4 "2026-01-09T22:06:02Z")

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Flaw #1: Overlapping copper pours causing shorts  
Flaw #2 noticed by @daniel.beeker: More than one ground

Thanks for playing!

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**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\
**Post date:** [January 12, 2026, 8:07pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/5 "2026-01-12T20:07:06Z")

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Personallty I would not call out the second flaw only due to net name. The 2 pin component that sits across those two nets might be a capacitor, resistor, or inductor and is most likely a required circuit element. That other net can be named anything and would not then be considered a flaw as long as the physical copper short does not exist.

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**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\
**Post date:** [January 12, 2026, 9:42pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-clue-its-overlapping/3786/6 "2026-01-12T21:42:26Z")

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Great, thanks for pointing that out! I’ll tell Dan.