# Should empty spaces on a 4-layer PCB be filled with ground? **URL:** \ **Category:** Design and Layout\ **Created:** [January 29, 2025, 2:31pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858 "2025-01-29T14:31:47Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![gigio](https://avatars.discourse-cdn.com/v4/letter/g/839c29/32.png) [@gigio](https://sierraconnect.protoexpress.com/u/gigio)\ **Post date:** [January 29, 2025, 2:31pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/1 "2025-01-29T14:31:47Z")
For a 4-layer PCB with the following stack-up: - Layer 1: High-speed signal - Layer 2: Dedicated ground plane - Layer 3: Power plane (5V, 3.3V, 1.8V) - Layer 4: Normal-speed signal On single/double-layer boards, the usual practice is to fill all unused space with ground. Since a dedicated ground plane already exists on Layer 2, is it still beneficial to fill the empty spaces on Layer 1 and Layer 4 with a ground pour? Would this improve signal integrity, or could it introduce potential issues? ---
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [January 29, 2025, 3:20pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/2 "2025-01-29T15:20:08Z")
These other threads are worth reading… > [@Ground Pouring Strategy for 4-Layer PCB Design](https://sierraconnect.protoexpress.com/t/ground-pouring-strategy-for-4-layer-pcb-design/1480): > > In my 4-layer PCB design featuring the SIGNAL/GND/POWER/SIGNAL stackup, I’ve opted against pouring ground-connected copper on the top and bottom signal layers. Since, I’ve come across suggestion, that adding ground on these external signal layers, while having a dedicated ground plane layer, may offer little benefit and could potentially lead to EMI issues. However, I’m encountering a dilemma regarding my I2S traces operating at approximately 12 MHz and the SD card interface traces running at 5… > [@Ground and Power Plane Considerations](https://sierraconnect.protoexpress.com/t/ground-and-power-plane-considerations/1241): > > After extensively researching the topic why it’s a bad idea to separate ground or power in mixed analog and digital circuits. I’ve decided to implement a 4-layer PCB design with full GND and VCC planes inside, and the signal routing outside. However, I’m still uncertain about the necessity and effectiveness of including a VCC plane. While some sources suggest that having separate GND and VCC planes, with a dielectric in between, can act as a decoupling capacitor, others argue for using two grou… > [@Ground Pour Considerations](https://sierraconnect.protoexpress.com/t/ground-pour-considerations/1171): > > Hello, I’m working on a 4-layer PCB with the top and bottom layers designated for signals and the inner two layers for ground and power. I’m adding ground pours on both the top and bottom layers to streamline the routing, but I’m concerned about potential issues, especially impedance, as my project involves USB C 2.0. In general I prefer to pour open areas with GND or PWR copper. ---
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [January 29, 2025, 3:29pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/3 "2025-01-29T15:29:20Z")
Note that your PWR layer is the return path for bottom layer signals. PWR layer is split voltages and routing bottom layer signals over PWR layer splits can cause EMI/signal intergrity issues as signal return paths should be to either GND or PWR of circuit that feeds that signal. Routing over a split that is not a direct PWR/GND source for that signal tends to create issues. This is when adding GND pour on the bottom layer can help improve signal return paths. However the exact circuit routing will determine how well this functions. ---
**Author:** ![will](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@will](https://sierraconnect.protoexpress.com/u/will)\ **Post date:** [February 11, 2025, 4:57pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/4 "2025-02-11T16:57:33Z")
Implementing ground pours on both the top and bottom layers remains beneficial even with an internal dedicated ground plane. These pours help ensure a low-impedance return path, which is vital for maintaining signal integrity, especially for high-speed signals. In cases where a continuous ground pour on the outer layers is challenging due to layout constraints, it is essential to use bridging vias to connect these pours to the internal ground plane. Placing these vias in available free spaces, such as board corners, further reinforces effective return paths without disrupting the overall design. ---
**Author:** ![jerrysaitter](https://avatars.discourse-cdn.com/v4/letter/j/c68b51/32.png) [@jerrysaitter](https://sierraconnect.protoexpress.com/u/jerrysaitter)\ **Post date:** [February 12, 2025, 2:11pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/5 "2025-02-12T14:11:41Z")
While a ground pour on Layers 1 and 4 can offer minor benefits, its impact is limited since Layer 2 already provides a robust ground plane. If you proceed with a ground pour, consider increasing the clearance gap between the pour and adjacent traces beyond standard settings. This improves manufacturability (e.g., reducing etching risks or shorts) without significantly compromising signal integrity. Avoid power pours for unused areas, as the multiple supply voltages on Layer 3 would complicate routing. Ultimately, prioritize maintaining a clean Layer 2 ground return path while balancing minimal outer-layer pours with practical manufacturing tolerances. ---
**Author:** ![JimJJewett](https://avatars.discourse-cdn.com/v4/letter/j/d78d45/32.png) [@JimJJewett](https://sierraconnect.protoexpress.com/u/JimJJewett)\ **Post date:** [February 13, 2025, 12:43am UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/6 "2025-02-13T00:43:53Z")
Both! Filling the empty space with a ground pour is helpful for all sorts of reasons, but maybe not _very_ helpful. If the improvement is less than a rounding error (and it might be), does it really count as an improvement? The down side is that it makes analysis and calculations harder, and getting them wrong can easily be worse than a rounding error. Is it worth the risk? Advantages include better copper balance, better shielding, more/wider return paths, larger charge reservoir for the reference, etc. These are important considerations, but usually they were already good enough before the pour. Will all those alternative return paths tempt you to get lazy/rushed and forget to verify that every particular preferred return path is unimpeded? (No gaps, no long detours, no pushing too much power through one small sliver…) The cases where this is easy to check tend to also be cases where the extra ground won’t help much either. If there are several extra pours, there are several extra verifications to make, so as to ensure that they aren’t floating and don’t form antennas and don’t allow loops in unfortunate locations. As for signal integrity in particular, did you already have calculations set up for a microstrip? They’ll be a little different for a co-planar waveguide. Even after making that adjustment, what happens when a trace goes near another feature, but there isn’t room for the ground pour to continue between them? ---
**Author:** ![JimJJewett](https://avatars.discourse-cdn.com/v4/letter/j/d78d45/32.png) [@JimJJewett](https://sierraconnect.protoexpress.com/u/JimJJewett)\ **Post date:** [February 13, 2025, 9:27pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/7 "2025-02-13T21:27:55Z")
I found almost all of [https://www.youtube.com/watch?v=xInazjL-c8U&ab\_channel=TexasInstruments](https://www.youtube.com/watch?v=xInazjL-c8U&ab_channel=TexasInstruments) really helpful, but they specifically discuss (and do some measurements on) the risks of a slightly botched ground pour specifically around 9:00. The “quiz” at the end gives an example board showing how easy it is to miss the problems – even specifically looking for them, I still missed the antenna finger. ---
**Author:** ![gigio](https://avatars.discourse-cdn.com/v4/letter/g/839c29/32.png) [@gigio](https://sierraconnect.protoexpress.com/u/gigio)\ **Post date:** [February 14, 2025, 7:01pm UTC](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858/8 "2025-02-14T19:01:50Z")
Thanks a lot Jim I’ll have a look at that!