# Polygons vs. Traces

**URL:** <https://sierraconnect.protoexpress.com/t/polygons-vs-traces/961>\
**Category:** Design and Layout\
**Created:** [January 30, 2024, 2:58pm UTC](https://sierraconnect.protoexpress.com/t/polygons-vs-traces/961 "2024-01-30T14:58:38Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Rilley](https://avatars.discourse-cdn.com/v4/letter/r/7ea924/32.png) [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\
**Post date:** [January 30, 2024, 2:58pm UTC](https://sierraconnect.protoexpress.com/t/polygons-vs-traces/961/1 "2024-01-30T14:58:38Z")

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When designing a 4-layer PCB, should I use polygons or traces for high currents in the inner layers? How do I decide when to use polygons and how to determine their width or area?

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**Author:** ![atar.mittal](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/atar.mittal/32/49_2.png) [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\
**Post date:** [January 30, 2024, 5:33pm UTC](https://sierraconnect.protoexpress.com/t/polygons-vs-traces/961/2 "2024-01-30T17:33:41Z")

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If it is a high current application then I think polygons are always preferable, the general rule being more current = more copper. There are occasional places where other factors (e.g. layer symmetry, sensitive traces that are too close and can’t be moved) may prevent it, but in terms of voltage drop, temperature rise, and noise issues, more copper is better copper (and also greener – less etching).