# PCB Glossary: Stitching Vias

**URL:** <https://sierraconnect.protoexpress.com/t/pcb-glossary-stitching-vias/4115>\
**Category:** PCB Glossaries\
**Created:** [June 4, 2026, 8:34am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-stitching-vias/4115 "2026-06-04T08:34:00Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Mohamed\_Faheemuddin](https://avatars.discourse-cdn.com/v4/letter/m/4da419/32.png) [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\
**Post date:** [June 4, 2026, 8:34am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-stitching-vias/4115/1 "2026-06-04T08:34:00Z")

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[Stitching vias](https://www.protoexpress.com/blog/how-via-stitching-facilitates-high-current-pcb-designs/?utm_source=sierraconnect&utm_medium=display&utm_campaign=glossary%2Bstitching%2Bvias%2Bjune%2B2026)are arrays of plated through-holes (PTHs) used to electrically connect copper pours, ground planes, or other features across multiple PCB layers. Unlike signal vias, they do not carry functional signals. Instead, they help maintain a low-impedance return path, reduce loop area for high-frequency currents, improve electromagnetic shielding, and enhance heat dissipation throughout the board.

 ![Stitching Vias](https://global.discourse-cdn.com/sierraconnect/original/1X/1fdf8601c6576c102f1882db2e3965aaaa05b9c4.jpeg)

Poor plane continuity forces return currents to take longer detour paths, which increases loop inductance, radiated emissions, and crosstalk susceptibility. Stitching vias resolves this by providing short, low-impedance vertical paths that keep return currents tightly coupled to their signal traces. They are essential in high-speed digital, RF, mixed-signal, and high-power designs.

**Implementation guidelines** :

- **Via spacing (pitch)**: Space stitching vias at regular intervals. For effective shielding and containment, use a pitch of λ/20 to λ/10 calculated using the highest significant harmonic frequency and the guided wavelength within the PCB dielectric material.
- **Ground connections** : Connect stitching vias directly to solid ground planes to provide short current-return paths. Avoid connecting them through narrow traces or thermal reliefs that introduce unwanted parasitic inductance.
- **Layer transitions (return vias)**: When a high-speed signal changes layers, place at least one ground via (transition via) immediately adjacent to the signal via. This maintains a continuous return path and prevents severe impedance discontinuities.
- **Plane assignment** : Ensure all stitching vias are explicitly tied to the correct reference plane. Floating or incorrectly assigned vias can create accidental shorts.
- **Shielding structures (via fences)**: To isolate RF circuits, antennas, or aggressive switching nodes, implement a multi-row via fence. Ensure the via pitch is tight enough to act as a solid conducting wall to the operating frequency range.
- **Antipad clearance** : Specify the required keep-out/antipad clearance on non-connected signal layers to prevent unintended shorts or excess parasitic capacitance.
- **Via dimensions** : Select drill and pad sizes that comfortably meet your fabricator’s minimum capabilities while providing adequate current-carrying capacity and mechanical reliability.
- **Density controls** : Excessive stitching vias can unnecessarily inflate manufacturing costs and cause fabrication issues, such as plating voids or drill wander issues in ultra-dense arrays. Always cross-reference your layout with the fabricator’s minimum via-to-via spacing rules.
- **Fabrication notes** : Clearly specify all stitching via requirements in your fabrication notes to avoid CAM misinterpretation. Explicitly call out which ground or power planes the stitching arrays are intended to tie together.