# Optimal Distribution of Vcc in a 4-Layer PCB Design **URL:** \ **Category:** Design and Layout\ **Created:** [April 11, 2024, 2:05pm UTC](https://sierraconnect.protoexpress.com/t/optimal-distribution-of-vcc-in-a-4-layer-pcb-design/1317 "2024-04-11T14:05:15Z")\ **Posts on this page:** 1\ **Showing post:** 4
**Author:** ![jonathan.lloyd.riley](https://avatars.discourse-cdn.com/v4/letter/j/3bc359/32.png) [@jonathan.lloyd.riley](https://sierraconnect.protoexpress.com/u/jonathan.lloyd.riley)\ **Post date:** [April 18, 2024, 8:08am UTC](https://sierraconnect.protoexpress.com/t/optimal-distribution-of-vcc-in-a-4-layer-pcb-design/1317/4 "2024-04-18T08:08:05Z")
You might find it useful to see the comments I made in this thread and the explanation for them as this relates directly to the concerns raised here. Follow the link and look for my reply. > [@Ground Pours considerations](https://sierraconnect.protoexpress.com/t/ground-pours-considerations/1297/6): > > If EMC matters, it is much better to make both of the two inner layers to be GND, and route the power on the signal layers. When you use copper pours on the signal layers they will now be to lower the impedance of the Power tracks. The reason why you want the two planes to be GND is because this is where the displacement currents from your signals flow. If your signals never change layer (top to bottom, or vice versa) it makes no difference what voltage is present on the plane, but the moment yo… --- _[View the full topic](https://sierraconnect.protoexpress.com/t/optimal-distribution-of-vcc-in-a-4-layer-pcb-design/1317)._