# Ground Plane Strategy for a 2-Layer PCB from an EMI/EMC Perspective **URL:** \ **Category:** Design and Layout\ **Created:** [October 13, 2025, 3:41pm UTC](https://sierraconnect.protoexpress.com/t/ground-plane-strategy-for-a-2-layer-pcb-from-an-emi-emc-perspective/3630 "2025-10-13T15:41:06Z")\ **Posts on this page:** 1\ **Showing post:** 2
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [October 13, 2025, 6:27pm UTC](https://sierraconnect.protoexpress.com/t/ground-plane-strategy-for-a-2-layer-pcb-from-an-emi-emc-perspective/3630/2 "2025-10-13T18:27:20Z")
1. Also read this thread: > [@Stack-Up Configurations for 2-layer and 4-layer PCBs](https://sierraconnect.protoexpress.com/t/stack-up-configurations-for-2-layer-and-4-layer-pcbs/1658): > > I am interested in learning about the stack-up configurations that others employ when designing 2-layer and 4-layer PCBs. For 2-layer PCBs, I typically utilize the top layer for signal and power traces, with a ground pour around the signal lines to reduce impedance. The bottom layer is dedicated entirely to ground. Although I have limited experience with 4-layer PCBs, my approach usually involves designating two layers as ground. For example, I might use a stack-up such as SIG/PWR—GND (core) S… --- _[View the full topic](https://sierraconnect.protoexpress.com/t/ground-plane-strategy-for-a-2-layer-pcb-from-an-emi-emc-perspective/3630)._